08:00-08:40   

Registation

08:40-09:00   

Opening & Welcome

09:00-10:00   

Keynote 1
Chair: Steve Furber

Neurogrid: A mixed-analog-digital multichip system for large-scale brain simulations
Kwabena Boahen
Stanford University

10:00-10:30   

Break

10:30-12:00   

Paper Session 1: Performance Analysis & Optimization
Chair: Mark Greenstreet

Statistical Analysis and Optimization of Asynchronous Digital Circuits
Tsung-Te Liu and Jan Rabaey
UC Berkeley

Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior
Mehrdad Najibi and Peter A. Beerel
University of Southern California

Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation
Andrey Mokhov,  Danil Sokolov,  Alex Yakovlev
Newcastle University

12:00-13:30   

Lunch

13:30-14:30   

Paper Session 2: Processor Case Studies
Chair: Marly Roncken

A Digital Neurosynaptic Core Using Event-Driven QDI Circuits
Nabil Imam¹,  Paul Merolla²,  John Arthur²,  Filipp Akopyan²,  Rajit Manohar¹,  Dharmendra Modha^2
1Cornell University, ²IBM Almaden

A Low Power Asynchronous GPS Baseband Processor
Benjamin Tang,  Stephen Longfield, Jr.,  Sunil Bhave,  Rajit Manohar
Cornell University

14:30-15:00   

Break

15:00-16:00   

Paper Session 3: Asynchronous Memories
Chair: Masashi Imai

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism
Naoya Onizawa¹,  Shoun Matsunaga²,  Vincent Gaudet¹,  Takahiro Hanyu^2
1University of Waterloo, ²Tohoku University

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery
James Garside,  Steven Furber,  Steven Temple,  David Clark,  Luis A. Plana
The University of Manchester

16:00-16:30   

Break

16:30-18:00   

Tutorial, Roundtable and Posters (parallel activities)

Tutorial: Asynchronous circuit performance analysis, fundamentals and efficient tool
Eslam Yahya¹, Laurent Fesquet² and Marc Reanudin^3
1American University in Cairo, Benha University, ²CIS Group, TIMA - CNRS - INPG – UJF, ³TIEMPO SAS

Roundtable: Designs on the Future in Asynchronous Circuits and Systems
Douglas Robinson, Aurelie Delemarle and Bernard Kahane

Posters: Bring your own poster
Works in progress / Wild and crazy ideas / Last-minute results / Ph.D. student projects / Industry posters / Demos not requiring elaborate setup

09:00-10:00   

Keynote 2
Chair: Ivan Sutherland

Biologically-Inspired Massively-Parallel Computing
Steve Furber
Univ. Of Manchester

10:00-10:30   

Break

10:30-12:00   

Paper Session 4: Synthesis and CAD
Chair: Jordi Cortadella

A Fast Hierarchical Approach to Resource Sharing in Pipelined Asynchronous Systems
John Hansen and Montek Singh
UNC-Chapel Hill

Uncle - An RTL Approach to Asynchronous Design
Robert Reese¹,  Scott Smith²,  Mitchell Thornton^3
1Mississippi State University, ²University of Arkansas, ³Southern Methodist University

A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits
Yvain Thonnart,  Edith Beigné,  Pascal Vivet
CEA-Leti, France

12:00-13:30   

Lunch

13:30-15:00   

Paper Session 5: Arithmetic Circuits
Chair: Erik Brunvand

Ultra Low Power Booth Multiplier Using Asynchronous Logic
Jiaoyan Chen,  Dilip Vasudevan,  Emanuel Popovici,  Michel Schellekens
University College Cork

An Asynchronous Floating-Point Multiplier
Basit Riaz Sheikh and Rajit Manohar
Cornell University

An Asynchronous Divider Implementation
Navaneeth Jamadagni¹ and Jo Ebergen^2
1Portland State University, ²Oracle Labs

15:00-15:30   

Break

15:30-16:30   

Paper Session 6: Industry Practice
Chair: Peter Beerel

Tiempo Asynchronous Circuits System Verilog Modeling Language
Renaudin Marc
TIEMPO

Introduction to Octasic Asynchronous Processor Technology
Michel Laurence
OCTASIC

17:00   

Bus to banquet

18:00   

Boat trip

19:00   

Banquet

09:00-10:00   

Keynote 3
Chair: Jan Madsen

Oticon hearing aids - highly optimized multi-processor systems on chip
Mogens Balsby
Oticon

10:00-10:30   

Break

10:30-12:00   

Paper Session 7: GALS and Signaling
Chair: John Bainbridge

DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems
Manoj Kumar Yadav,  Mario Roberto Casu,  Maurizio Zamboni
Politecnico di Torino

Performance analysis of GALS datalink based on pausible clocking scheme
Xin Fan,  Milos Krstic,  Eckhard Grass
IHP Microelectronics

PID (Partial Inversion Data): an M-of-N Level-Encoded Transition Signaling Protocol for Asynchronous Global Communication
Marco Cannizzaro and Luciano Lavagno
Politecnico di Torino

12:00-13:00   

Lunch

13:00-14:00   

Paper Session 8: Fault Tolerance
Chair: Andreas Steininger

Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects
Julian Pontes¹,  Pascal Vivet²,  Ney Calazans^1
1PUCRS, Brazil, ²CEA-Leti, France

Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes
Benjamin Devlin,  Makoto Ikeda,  Kunihiro Asada
The University of Tokyo

14:00-14:30   

Best Paper Award & Closing