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Wednesday May 9, 2012

08:00-08:40    Registration

08:40-09:00    Opening and Welcome

09:00-10:00    Keynote 1 Chair: Jan Madsen

Oticon hearing aids - highly optimized multi-processor systems on chip Mogens Cash Balsby Oticon Slides

10:00-10:30    Break

10:30-12:15    Paper Session 1: Routing and Arbitration Chair: Radu Marculescu

MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect Chris Fallin , Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu Carnegie Mellon University Slides

Deja Vu Switching for Multiplane NoCs Ahmed Abousamra, Rami Melhem, Alex Jones University of Pittsburgh Slides

Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks Masoumeh Ebrahimi1, Masoud Daneshtalab1, Hannu Tenhunen1, Maurizio Palesi2 1University of Turku, 2University of Kore Slides

Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip Danella Zhao, Ruizhe Wu University of Louisiana at Lafayette Slides

12:15-13:30    Lunch

13:30-14:45    Paper Session 2: Power Modeling and Power Management in NoCs Chair: Axel Jantsch

An Optimal Control Approach to Power Management for Multi-VFI Platforms Paul Bogdan 1, Rafa Tornero2, Radu Marculescu1 1Carnegie Mellon University, 2University of Valencia Not available

In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches Xi Chen1, Zheng Xu1, Hyungjun Kim1, Paul Gratz1, Jiang Hu1, Michael Kishinevsky2, Umit Ogras2 1Dept. of ECEN, Texas A&M University, 2Intel, Strategic CAD Labs Slides

Modeling and Power Evaluation of On-Chip Router Components in Spintronics Pierre Schamberger1, Zhonghai Lu1, Xianyang Jiang2, Meikang Qiu3 1KTH The Royal Institute of Technology, Sweden,2Wuhan University, China, 3University of Kentucky, USA Slides

14:45-15:15    Break

15:15-18:15    Tutorials (tutorials in parallel, participants select one)

Methods for Fault Tolerance in Networks on Chip Axel Jantsch1, Martin Radetzki2 1KTH The Royal Institute of Technology, Sweden,2University of Stuttgart, Germany Not available

Switch design: A unified view of microarchitecture and circuits Giorgos Dimitrakopoulos Democritus University of Thrace, Kimmeria Campus, Xanthi, Greece Slides

Thursday May 10, 2012

08:45-09:45    Keynote 2 Chair: Ran Ginosar

Design of 3D Specific Systems: Prospectives and Interface Requirements Paul Franzon North Carolina State University, USA Slides

09:45-10:15    Break

10:15-12:00    Paper Session 3: Novel NoC Design & Support for CMP/MPSoCs Chair: Paul Gratz

Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support Mario Lodde1, Jose Flich1, Manuel Acacio2 1Universitat Politècnica de València, 2Universidad de Murcia Slides

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers Stavros Volos, Ciprian Seiculescu, Boris Grot, Naser Khosro Pour, Babak Falsafi, Giovanni De Micheli EPFL Slides

Synthesis of NoC Interconnects for Custom MPSoC Architectures Gul Khan, Anita Tino Ryerson University Slides

Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations Snaider Carrillo1, Jim Harkin1, Liam McDaid1, Fearghal Morgan2, Sandeep Pande2, Seamus Cawley2, Brain Mc Ginley2 1University of Ulster, 2National University of Ireland Slides

12:00-14:00    Lunch (Wednesday posters from 13:15-14:00)

14:00-15:15    Paper Session 4: Simulation and Analysis Chair: Steven Nowick

Reservation-based Network-on-Chip timing models for large-scale architectural simulation Javier Navaridas1, Behram Khan1, Salman Khan1, Paolo Faraboschi2, Mikel Luján1 1The University of Manchester, 2HP Labs Slides

TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputer Pablo Abad, Pablo Prieto, Lucia Gregorio, Valentin Puente, Jose-Angel Gregorio Universisty of Cantabria Slides

Analytical Performance Modeling of Hierarchical Interconnect Fabrics Nikita Nikitin, Javier de San Pedro, Josep Carmona, Jordi Cortadella Universitat Politecnica de Catalunya Slides

15:15-15:45    Break

15:45-17:00    Paper Session 5: Flow control and flit serialization Chair: John Bainbridge

Dynamic Flow Regulation for IP Integration on Network-on-Chip Zhonghai Lu, Yi Wang KTH Royal Institute of Technology, Sweden Slides

A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip Changlin Chen1, Ye Lu2, Sorin Cotofana1 1Delft University of Technology, 2Queen's University of Belfast Slides

Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels Robert Hesse, Natalie Enright Jerger University of Toronto Slides

17:00-18:00    Posters (Thursday posters session)

18:00    Bus to Tivoli

Friday May 11, 2012

08:45-10:30    Session 6: QoS, Error Control and Verification Chair: Cristina Silvano

Efficient Timing Channel Protection for On-Chip Networks Yao Wang, Edward Suh Cornell University Slides

A Statically-Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems Martin Schoeberl, Florian Brandner, Jens Sparsø, Evangelia Kasapaki Technical University of Denmark Slides

A Mixed Verification Strategy Tailored for Networks on Chip Georgios TSILIGIANNIS, Laurence PIERRE TIMA Slides

Transient and Permanent Error Control for High End Multiprocessor Systems-on-Chip Qiaoyan Yu1, José Cano2, José Flich2, Paul Ampadu3 1University of New Hampshire, 2Universitat Politècnica de Valencia, 3University of Rochester Slides

10:30-11:00    Break

11:00-12:30    Special Session (Industrial Platform Perspectives) Chair: Davide Bertozzi

SoC implementation-Driven Interconnect Design Gilles Baillieu Arteris Not available

Interconnect Challenges and Trade-offs in the Deep Submicron Era for Platform 2012 stackeable many core accelerator Eric Flamand STMicroelectronics Not available

Beyond the GHz NoC: Challenges in Designing High-Performance Mobile SoCs John Bainbridge Sonics Not available

Network-on-Chip Research for Cache-Coherent CMPs Kumar Akhilesh Intel Not available

12:30-13:45    Lunch

13:45-15:30    Paper Session 7: 3D & Emerging NoCs Chair: Chrys Nicopoulus

Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures Amir-Mohammad Rahmani1,2, Kameswar Rao Vaddina1,2, Khalid Latif1,2, Pasi Liljeberg1, Juha Plosila1, Hannu Tenhunen1,3 1University of Turku, Finland, 2Turku Centre for Computer Science, Finland, 3Royal Institute of Technology, Sweden Slides

Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints Luca Ramini1, Davide Bertozzi1, Luca P. Carloni2 1University of Ferrara, 2Columbia University Slides

A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects Hyunjun Jang, Baik Song An, Nikhil Kulkarni, Ki Hwan Yum, Eun Jung Kim Texas A&M University Slides

DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic MIT Slides

15:30-16:15    Break and Poster (Friday posters)

16:15-16:30    Best Paper Award & Closing