With shrinking process geometries, boundary effects play an important role. Typically, boundary effects are due to fringing or anisotropic photolithographic processing near the discontinuities of structures of the layout. During design and layout, structures are considered as two-dimensional. In reality, the structures are three-dimensional. Fringing effects are particularly important for transistors and well resistors, whereas, anisotropic photolithographic processing is a general problem.
With larger geometry processes (
), such boundary effects could
be ignored. However, for modern process dimensions (1.0 to 
)
such effects cause major errors.
Figure 2.10: Cross section of four transistors.
In Figure 2.10, the cross section of four transistors from
a precision current mirror is shown. Due to differences in the growth rate
of the field oxide thickness for narrow strips of field oxide and larger
field oxide areas
, the field oxide between the transistors
can be marginally thinner than the field oxide at the edge of the transistor
structure. The thinner field oxide between the transistors results in an
effective channel width difference between the transistors M2, M3 and M1, M4.
The difference in channel widths implies mismatch between precision matched current sources, as transistors M1 and M4 delivers a different current from the transistors M2 and M3. This effect can be fully eliminated with the use of dummy structures. The matching of the transistors M1-M4 can be improved by physically placing a dummy transistor to the left and a dummy to the right of the entire structure. The dummies are not to be used in the circuit. Then, each of the transistors M1-M4 have similar boundary conditions.
Similarly, dummy structures can be used in the realisation of resistors and capacitors. Dummy elements also serve to prohibit or at least reduce the effects of anisotropic processing. Dummy elements are used to provide all active elements with similar boundary conditions. The dummy structures require relatively little area and may yield a dramatic improvement in the element matching achieved.
Figure 2.11: Well resistor structure.
Figure 2.11 shows two possible layouts of a well resistor.
Both implementations would function correctly, if the well could be
considered to be a two-dimensional structure. The impedance of the well
in Figure 2.11 is given by:
However, the three-dimensional properties of the well influences on the
resistance, and both ends of the well resistor has a slightly higher
impedance. The impedance can be as high as
150% of the normal sheet resistance.
The first realisation shown in Figure 2.11 incorporates
the full effect of the curvature in the resistor. As a consequence, the
expression in Equation 2.17 can not be used to calculate
the resistance value. The first realisation has a further disadvantage.
A misalignment of the N+ diffusion well contact with respect to the well
causes the contact to move further into the area of curvature, resulting
in a change in the resistor value. Both problems are easily solved by
extending the well sufficiently beyond the N+.
Figure 2.12: Stress distribution in <100> silicon due to pressure.
The orientation of precision elements should be considered as well. Matched elements should always be drawn with the same orientation, and should not be rotated with respect to one another. Pressure on silicon results in an anisotropic stress distribution due to the crystal structure. Figure 2.12 shows the stress distribution of pressure for <100> silicon. The Figure shows that the pressure distortion in X and Y is different. If matched elements were laid out with different orientations, these elements would experience different degrees of stress from pressure on the die. This differential stress gives rise to an effective mismatch of the elements. For example, the pressure on the silicon die in a plastic package can be as high as 200 bar[Mal94]. Effective mismatch of elements up to 5% have been observed under such conditions.
Figure 2.13: Matched elements with temperature contours.
The orientation of matched elements with respect to power dissipation
elements on an IC is equally important. Power dissipation on the chip
causes temperature gradients, and for elements with a temperature
dependence such a gradient will causes a
change in the element value. To avoid a mismatch of the elements due
to the temperature gradient, the element should be laid out symmetric
to the main power dissipation elements. In Figure 2.13,
two groups of resistors are laid out with respect to a power dissipation
element. The resistor group A will have a mismatch, as the resistors are
at different temperatures. The resistors in group B are symmetrically
laid out with respect to the power dissipation and have the same average
temperature. As a result, no error due to temperature mismatch occurs.
The number and diversity of boundary effects is so large that it is not possible to describe all such effects. The understanding and prediction of such effects requires detailed knowledge of the process used. Awareness and understanding of the problem is the key.