Figure 6.8: Interconnection coupling.
Finally, noise can be coupled into a signal line. If an analog signal is routed parallel to a digital signal, then noise is coupled from the digital signal to the analog signal through the mutual capacitance. Figure 6.8 illustrates interconnection coupling. To prevent this type of coupling, horizontal shielding should be used. The placement of an analog ground line between the digital and analog signal functions to decouple the two lines. To minimise the likelihood of parasitic coupling, the analog interconnections should be kept as short as possible.
Figure 6.9: Layout of switched capacitor switch.
For switched capacitor circuits, charge injection through the switches
is a major concern. Figure 6.9 a) shows a transmission gate design
typical of switched capacitor applications. The clock lines 
and
control the operation of the switches. At every clock transition,
an amount of charge (proportional to the area of the gate) is capacitively
coupled from the clock lines to the outputs of the switches
.
Figure 6.9 b) shows an improved layout for this cell. The sizes of the clocked transistors have been reduced to the minimum acceptable value. The smaller the transistor dimensions, the smaller the injected charge. Unfortunately, the switch transistors can not always be used with minimum geometries, because of the resulting RC delays in the switched capacitor circuit.
Finally, Figure 6.9 c) shows a further improvement of the layout
with respect to clock feedthru. The clock lines and
are routed over the first set of transistors, not over the analog signal
lines a and c. This reduces the parasitic capacitance between the clock
and the analog signals.