Cascode current mirrors

In Section 4.2, we found that the output impedance of the simple MOS current mirror was limited. For a current output, we require an infinite output impedance. In this Section, we will discuss a frequently used method for increasing the output impedance, the cascode.

  
Figure 4.4: ^a) A cascode transistor, ^b) a self-biased cascode current mirror, and ^c) a cascode current mirror with separate generation of the cascode voltage.

Figure 4.4(a) illustrates the basic cascode configuration, in which two MOS transistors are used to realise an `improved' transistor. The transistor M₁ realises the required transistor function, converting the input voltage, V_G, to an output current, I_DS. The operating point must be chosen, such that M₁ operates in saturation. The second transistor, the cascode transistor M₂, must maintain a fixed voltage over M₂, independent of the voltage of the output node. In this way, the channel length modulation of M₁ is reduced, and the current is less dependent of the voltage, V_D, at the output node.

As M₁ must be in saturation, the requirements are:

Similarly, M₂ operates in saturation, and the following requirement can be calculated for the cascode voltage, V_CAS:
 
Finally, still using that M₂ operates in saturation, the voltage V_D at the output of the cascode configuration, is required to be:
 

Figure 4.4(b) shows a self-biased cascode current mirror. The transistor pair M_1B and M_2B is cascode configured, and transistors M_1A and M_1B constitute a simple current mirror. The term `self-biased' is motivated as follows. The cascode voltage is generated automatically by the added input transistor M_2A. The cascode voltage can be calculated as follows:

Inserting the cascode voltage in the Requirement (4.25) and noting that according to Equation (4.6):

The transistors M_2A and M_2B are often designed to have the same effective gate voltage, V_GS-V_T. The transistors are scaled relative to their currents. Thus, the requirement is met within a margin of one threshold voltage. When we consider Equation (4.26), we note that this relatively large margin implies, that the useful voltage swing at the output is reduced by this margin. The later can be considered the price to pay for the `free' cascode voltage of the self-biased cascode current mirror.

Figure 4.4(c) shows a cascode current mirror with separate generation of the cascode voltage, V_CAS. In this configuration, V_CAS can be selected freely. If the useful voltage swing is required as large as possible, a small V_CAS should be selected according to Equation (4.26). At the same time, V_CAS should exceed the limit in Equation (4.25). In the example, V_CAS is generated by a single diode coupled transistor, M_CAS, which conducts the current I_IN'. According to Equation (3.2):

Combining this with Equation (4.25) results in:

The of the cascode transistors is assumed to be scaled with respect to the current.

In the following, a small signal analysis of the cascode configuration will be used to determine the output conductance. Figure 4.5(a) illustrates the cascode configuration, and Figure 4.5(b) a small signal equivalent diagram of the configuration. In the analysis, we consider V_GS and V_CAS at a constant voltage (small signal ground). An output current i_out is applied, and the output voltage v_out observed. The analysis is illustrated in the simplified small signal equivalent diagram in Figure 4.5(c).

  
Figure 4.5: ^a) Cascode transistor, ^b) small signal equivalent diagram, and ^c) reduced small signal equivalent diagram.

The applied current must pass g_ds1, and the voltage must be:

Kirchoff's current law for the output node now results in:
 
A₀₂ denotes the DC-amplification of M₂ as discussed in Section 3.4. Comparing this result to the output impedance of a single transistor, (1/g_ds1), we realise that the cascode increases the output impedance by an amount dominated by A₀₂. As illustrated in Figure 3.6, typical values of A₀₂ may lie in the range 50-100. Thus, the cascode realises a significantly higher output impedance.

The compact layout of cascode transistors is illustrated in Figure 4.6. The simple layout in Figure 4.6(b) is 10.515.0, whereas the compact layout in Figure 4.6(c) measures 10.59.0. The area is reduced by 40% using typical design rules for a 1 CMOS process.

  
Figure 4.6: ^a) Cascode transistor diagram, ^b) simple layout, and ^c) compact cascode transistor layout.

The compact layout has the further advantage that the parasitic capacitance at the common node is reduced. The diffusion area is reduced from 57.75 to 15.75, and the perimeter is reduced from 53 to 24.