Figure 4.3 shows a current mirror loaded by resistance R_{L} at the output. The corresponding small signal equivalent diagram is also shown in the Figure.
Figure 4.3: ^{a)} MOS current mirror with load, and ^{b)} the
corresponding small signal equivalent diagram.
In this Section the high frequency properties are analysed. Therefore, channel length modulation is disregarded. The following assumptions will be used in the analysis:
The output related pole, p_{2}, is usually not considered as belonging to the current mirror. Rather, the output capacitance, c_{bd2}, is considered among all other parasitic capacitances on the output node. According to Equation (4.16), this capacitance is inversely proportional to the square of V_{IN}-V_{T}. Therefore, a `large' effective gate voltage may be selected, if the capacitance on the output node is considered critical.
The real limiting factor of the current mirror is the pole p_{1}. determines the 3dB-frequency of the current mirror. According to Equation (4.22), the 3dB-frequency is the unity-gain frequency of M_{1} given by Equation (3.22), divided typically by a factor 2+B. As discussed in Section 3.4, is maximised using minimum channel lengths and `large' effective gate voltages, V_{GS}-V_{T}. From Figure 3.6, 3dB-frequencies around 1GHz may be obtained using B=1 and minimum channel lengths in a process.
The discussion recommends `large' effective gate voltages, V_{IN}-V_{T}. However, this does not come for free. According to Equation (4.4), the effective gate voltage is identical to the minimal useful voltage over the current mirror output. Therefore, a `large' effective gate voltage limits the voltage swing at the current mirror output.