Small signal analysis of the MOS current mirror

Figure 4.3 shows a current mirror loaded by resistance R_L at the output. The corresponding small signal equivalent diagram is also shown in the Figure.

  
Figure 4.3: ^a) MOS current mirror with load, and ^b) the corresponding small signal equivalent diagram.

In this Section the high frequency properties are analysed. Therefore, channel length modulation is disregarded. The following assumptions will be used in the analysis:

• I_IN, I_OUT, the common gate-source voltage V_IN, and the common channel length L will be considered as independent variables. Then, W₁ and W₂ will become functions of these variables, and the results may be interpreted as functions of the independent variables.
• The capacitance of the drain diffusion is considered proportional to W:
   
  L_S/D denotes the length of the source/drain diffusion, and V_BD denotes some `representative' voltage. Using the values in Table 3.1, , and V_BD=-1V, we can calculate C_jW=1.26nF/m.

The channel widths of the transistors is calculated from Equation (3.2):

The parasitic capacitances are obtained using Equation (4.10) and Figure 3.5:
  
Finally, the DC parameters of the transistors are calculated using the expressions in Figure 3.5:
 
We have now determined the values of all the components in Figure 4.3. We may now proceed to analyse the small signal equivalent diagram. For the input node, Kirchoff's current law yields
 
Similarly, for the output node, we get:
 
From Equations (4.19-4.20), the current mirror transfer function is determined:

Apparently, the current transfer function of the current mirrors has two poles, an internal pole p₁ related to the input node, and a load dependent pole p₂. The poles are calculated using Equations (4.13-4.18):
 

The output related pole, p₂, is usually not considered as belonging to the current mirror. Rather, the output capacitance, c_bd2, is considered among all other parasitic capacitances on the output node. According to Equation (4.16), this capacitance is inversely proportional to the square of V_IN-V_T. Therefore, a `large' effective gate voltage may be selected, if the capacitance on the output node is considered critical.

The real limiting factor of the current mirror is the pole p₁. determines the 3dB-frequency of the current mirror. According to Equation (4.22), the 3dB-frequency is the unity-gain frequency of M₁ given by Equation (3.22), divided typically by a factor 2+B. As discussed in Section 3.4, is maximised using minimum channel lengths and `large' effective gate voltages, V_GS-V_T. From Figure 3.6, 3dB-frequencies around 1GHz may be obtained using B=1 and minimum channel lengths in a process.

The discussion recommends `large' effective gate voltages, V<sub>IN</sub>-V<sub>T</sub>. However, this does not come for free. According to Equation (4.4), the effective gate voltage is identical to the minimal useful voltage over the current mirror output. Therefore, a `large' effective gate voltage limits the voltage swing at the current mirror output.