Capacitances of the small-signal equivalent diagram

The presented MOS transistor model is not sufficiently accurate at higher frequencies: Capacitances influence the circuit response. A detailed analysis of all relevant capacitances of the MOS transistor is extremely complicated. The results will be examined for use in small-signal analysis of analog CMOS circuits.

  
Figure 3.3: A MOS transistor cross section along the channel.

Figure 3.3 shows a cross section of a N-channel MOS transistor with relevant capacitances. A general problem in relation to this analysis is that many of these capacitances are distributed. The conductive channel forms one of the ``plates'' in relation to two different capacitances: the gate-channel capacitance and the substrate-channel capacitance. In order to use the MOS transistor model for circuit analysis, these distributed capacitances must be split into two discrete parts connected to each end of the conducting channel, i.e. source and drain. In this connection we will use the parameter :
 

The gate capacitance of the MOS transistor is distributed between source and drain as follows:

The capacitance of the depletion area under the channel is distributed into source, drain and gate according to the following expressions:

The capacitances of the source and drain diffusions are calculated according to these expressions:

where C_j0 is the capacitance per unit area of an unbiased diffusion, C_jp0 is the capacitance per unit perimeter of an unbiased diffusion, is the ``built-in potential'' (in the order of 0.5-1.0V), and m and mp are process characteristic parameters. (Typical values of m and mp are 1/3-1/2). A_S and A_D are the areas of the source drain diffusions, respectively, while P_S and P_D are the respective perimeters of the source and drain diffusions. As source and drain diffusions extend under the gate, as illustrated in Figure 3.3, small overlap capacitances will appear between gate and source/drain. These capacitances are given by
  
where L_D is the overlap appearing between the gate polysilicon and the source/drain diffusions.

  
Figure 3.4: Complete small signal equivalent diagram.

Figure 3.4 shows a small signal equivalent diagram with all capacitances.