Tutorials
NOCS 2012
Asynchronous circuit performance analysis, fundamentals and efficient tool
Presenters:
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•Eslam Yahya, American University in Cairo AUC, Benha University, Egypt, dr.eslam.yahya@gmail.com
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•Laurent Fesquet,CIS Group, TIMA - CNRS - INPG – UJF, Grenoble, France, laurent.fesquet@imag.fr
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•Marc Reanudin, TIEMPO SAS, Grenoble, France, marc.renaudin@tiempo-ic.com
Keywords and scope of the tutorial:
Asynchronous Circuit, Performance Analysis and Optimization, Process Variability.
Abstract:
This tutorial covers the problem of performance modeling, analysis and optimization of asynchronous circuit. A survey of the state of the art is given and then AHMOSE tools and the underlying methods are introduced. These tools use circuit level abstraction to provide accurate statistical static performance analysis for asynchronous circuits.
Here are some ideas which will be covered in the tutorial:
1) Statistical Timing analysis of asynchronous circuits including conditional structures. All analysis are done while considering delay variability.
2) Analyzing the power and EMI characteristics.
3) Studying the effect of handshaking protocol on different performance metrics.
4) Automatically optimize asynchronous structures by optimally place registers to meet the required cycle time.
Presenters’ biography:
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•Eslam Yahya received his engineering BSc in and MSc in Microelectronics respectively in 2000 and 2005 from Benha University, Egypt. In 2001, he received a diploma in VLSI and EDA from ITI, Egypt, and then he joined ITI and Mentor Graphics as a senior researcher to work on VLSI and signal processing. He joined IRISA, INRIA, France as a research fellow in 2002, where he worked on data security and crypto processors. In 2005, he joined TIMA laboratory, France for his PhD; where he received the PhD in Micro-Nano Electronics in 2009. The PhD work focuses on asynchronous circuits and systems. After his PhD, he joined TIMA as a research associate. 2010, he returned to Egypt to join Nile university and Benha University as assistant professor. In 2011, he joined the American university in Cairo “AUC” as assistant research professor and he established the asynchronous research team. His current research activities include design and optimization of asynchronous circuits; embedded systems; security; asynchronous oscillators; 3D ANOCs and CAD tools.
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•Laurent Fesquet received the M.Eng. degree in physics from the Ecole Nationale Superieure de Physique, Strasbourg, France, in 1993, the M.S.degree in applied physics from the Ecole Normale Superieure, Cachan, France, in 1994, and the Ph.D. degree in electrical engineering from Paul Sabatier University, Toulouse, France, in 1997. In 1995, he was a Lecturer in charge of electronics and inertial navigation systems with the French Navy Instruction Center. In 1999, he joined the Grenoble Institute of Technology, Grenoble, France, as an Associate Professor. Since 2008, he is the Deputy Director of CIME Nanotech, an academic center that supports microelectronic teaching and research activities. His current research at the TIMA Laboratory includes asynchronous circuit design, computer-aided design (CAD) tools, and non-uniform signal processing.
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•Marc Renaudin received the Engineering and PhD degrees in microelectronics and signal processing from the Institut National Polytechnique de Grenoble, France, respectively in 1987 and 1990. From 1990 to 1998, he served as an assistant professor at Telecom Bretagne, France, a Graduate School of Telecommunications Engineering where he was in charge of the Grenoble entity. In 1998, he joined Grenoble INP as a Professor and he founded the Concurrent Integrated Systems Group at Tima Labs where he carried out research work on asynchronous circuit design and associated CAD tools. In 2007, Professor Marc Renaudin co-founded Tiempo, a startup company located in Montbonnot St-Martin, near Grenoble (France), and became its CTO. Tiempo is developing complete solutions – IPs and EDA tools – for the design of innovative asynchronous delay insensitive integrated circuits that are ultra-low power, ultra-low noise, variability-tolerant and secured against attacks by power analysis and fault injections.