On this page, you find a set of fictitious, simplified design rules for a generic 0.18µm CMOS process. The rules are representative of a typical 0.18µm CMOS process. Several layers, typical of similar processes, have been omitted from these rules, leaving behind a simplified set of design rules. However, the rules and the electrical parameters may only be used for educational purposes.
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Design rules for a typical 0.18µm CMOS process: o Geometrical design rules (simplified) Electrical parameters: o Electrical parameters for active devices o Electrical parameters for wires o Vertical topologies Drawings: o Cross section (not drawn to scale) |
The design rules and the electrical parameters described in this section are fictitious. Any resemblance to a specific process of any single semiconductor fabline is accidental.
In no event shall any person or organization of people be held responsible for any direct or indirect, incidental or consequential damages or loss of profits from the use of the informations stated in this document or from its connections to other Internet services.
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Faults in Design rules: o Recorded Faults |
