Design of Power Efficient FPGA based Hardware Accelerators |
| | Abstract | The aim of this thesis is to use an FPGA to speed up computations, and to analyse performance trade-offs with respect to latency, throughput and energy consumption.
To do this an option pricing algorithm was chosen as the test case. The pricing algorithm was implemented in C and the latency tested on a desktop PC.
Then a soft core processor system was implemented, to run the application and to measure the number of cycles it took to do the calculations of option pricing. The third experiment involved a Application Specific Processor, designed to implement the option pricing algorithm in hardware.
The latency of these systems was measured, and the power consumption was measured for the soft core processor and the ASP.
Finally the three systems were compared with respect to their individual energy consumption. The results clearly show a speed up when comparing Application Specific processors with CPUs, both desktop CPU and soft core processors. The energy consumption was also lower for the ASP and when using ASPs in parallel an even greater reduction is achieved. | | Type | Master's thesis [Academic thesis] | | Year | 2012 | | Publisher | Technical University of Denmark, DTU Informatics, E-mail: reception@imm.dtu.dk | | Address | Asmussens Alle, Building 305, DK-2800 Kgs. Lyngby, Denmark | | Series | IMM-M.Sc.-2012-133 | | Note | DTU supervisor: Alberto Nannarelli, an@imm.dtu.dk, DTU Informatics | | Electronic version(s) | [pdf] | | Publication link | http://www.imm.dtu.dk/English.aspx | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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