@MASTERSTHESIS\{IMM2012-06485,
    author       = "J. S. Hegner",
    title        = "Design of Power Efficient {FPGA} based Hardware Accelerators",
    year         = "2012",
    school       = "Technical University of Denmark, {DTU} Informatics, {E-}mail: reception@imm.dtu.dk",
    address      = "Asmussens Alle, Building 305, {DK-}2800 Kgs. Lyngby, Denmark",
    type         = "",
    note         = "{DTU} supervisor: Alberto Nannarelli, an@imm.dtu.dk, {DTU} Informatics",
    url          = "http://www.imm.dtu.dk/English.aspx",
    abstract     = "The aim of this thesis is to use an {FPGA} to speed up computations, and to analyse performance trade-offs with respect to latency, throughput and energy consumption.
To do this an option pricing algorithm was chosen as the test case. The pricing algorithm was implemented in C and the latency tested on a desktop {PC}.
Then a soft core processor system was implemented, to run the application and to measure the number of cycles it took to do the calculations of option pricing. The third experiment involved a Application Specific Processor, designed to implement the option pricing algorithm in hardware.
The latency of these systems was measured, and the power consumption was measured for the soft core processor and the {ASP}.
Finally the three systems were compared with respect to their individual energy consumption. The results clearly show a speed up when comparing Application Specific processors with CPUs, both desktop {CPU} and soft core processors. The energy consumption was also lower for the {ASP} and when using ASPs in parallel an even greater reduction is achieved."
}