Lectures 4 through 6: CMOS logic performance estimation

Lecture 4: CMOS delay

Purpose: How to estimate CMOS logic gate delay and to dimension a multi-stage network

Contents:

RC delay models and Elmore delay model
Logical and electrical effort and parasitic delay
2^nd-order effects
CMOS inverter propagation delay
CMOS gate delay and multi-stage logic networks

Literature:

Weste & Harris sections 4.1 - 4.3

Supplementary reading:

J.M. Rabaey, A. Chandrakasan and B. Nikolic:
Digital Integrated Circuits - A Design Perspective,
2^nd edition, Prentice Hall, 2003,
Section 6.2

Lecture 5: Resistance, capacitance and wire models

Purpose: To describe how to estimate internal parasitics

Contents:

MOS transistor intrinsic: overlap, channel, diode capacitances
Wiring: substrate, inter-wiring capacitances
Miller effect
Sheet resistances
Transistor-'ON', diffusion, contact, wire resistances
Wire delay: Lumped-RC, distributed-RC models
Elmore delay model

Literature:

Weste & Harris sections 4.5 - 4.6
Design Rules for a 90 nm CMOS process

Supplementary reading:

J.M. Rabaey, A. Chandrakasan and B. Nikolic:
Digital Integrated Circuits - A Design Perspective,
2^nd edition, Prentice Hall, 2003,
Sections 3.3.2 - 3.3.4, 4.1 - 4.4, 5.4

Lecture 6: Power consumption, technology scaling and process variations

Purpose: To estimate the power consumption of the CMOS inverter

Contents:

Activity-related and short-circuit dynamic power consumption
Static power consumption: leakage currents, sub-treshold losses
Design margin
Reliability
Technology scaling

Literature:

Weste & Harris sections 4.4, 4.7 - 4.9

Supplementary reading:

J.M. Rabaey, A. Chandrakasan and B. Nikolic:
Digital Integrated Circuits - A Design Perspective,
2^nd edition, Prentice Hall, 2003,
Sections 5.5

Keith Sabine:
A methodology for minimizing leakage current,
EEdesign, CMP Media, October 2003

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Associate professor Flemming Stassen, stassen@imm.dtu.dk

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