FPGA Prototyping of Asynchronous Networks-on-Chip |
Jon Neerup Lassen
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| Abstract | Network-on-chip (NoC) is an emerging paradigm for handling the communication in large system-on-chips. This project investigates the ability to prototype asynchronous NoCs on FPGAs.
The implementation of asynchronous circuits on standard FPGAs is highly experimental, therefore the first part of the project has been to establish a design flow for the implementation of asynchronous circuits on FPGAs. In the project an asynchronous best-effort NoC for an FPGA has been successfully developed. The NoC implementation consists of a router and network adapters and is implemented using a 4-phase bundled data handshake protocol. Cores connects to the network using an OCP interface. To demonstrate the NoC it has been implemented in a small multi-processor prototype using a mesh topology for the network. |
| Type | Master's thesis [Academic thesis] |
| Year | 2008 |
| Publisher | Technical University of Denmark, Department of Applied Mathematics and Computer Science |
| Address | Richard Petersens Plads, Building 324, DK-2800 Kgs. Lyngby, Denmark, compute@compute.dtu.dk |
| Series | DTU Compute M.Sc.-2008-26 |
| Note | |
| Electronic version(s) | [pdf] |
| Publication link | http://www.compute.dtu.dk/English.aspx |
| BibTeX data | [bibtex] |
| IMM Group(s) | Computer Science & Engineering |