Accelerating Instruction Set Emulation using Reconfigurable Hardware and Trace Based Optimization |
Andreas Erik Hindborg
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| Abstract | The speed of instruction set emulation is essential when researching new instruction sets or changes to current instruction sets. It is also essential when
executing programs for which the originally targeted platform is no longer available.
Software-based instruction set emulators are used extensively in computer architecture development. They allow researchers to evaluate performance implications of changes to the instruction set without going through the effort
of implementing the instruction set in silicon. They also allow software developers to develop and debug software for hardware architectures for which the hardware model is not yet finished. However, there is an inherent limit to the amount of instructions that can be emulated in a given time frame for emulators implemented in software.
This report presents a method to implement instruction set emulation by using a reconfigurable hardware accelerator combined with a conventional processor. A significant part of the proposed system is designed and implemented. The system aims to emulate the Motorola 68000 instruction set. The hardware part of the implemented solution is capable of operating at a clock frequency of 237 MHz. |
| Type | Master's thesis [Academic thesis] |
| Year | 2013 |
| Publisher | Technical University of Denmark, Department of Applied Mathematics and Computer Science |
| Address | Matematiktorvet, Building 303B, DK-2800 Kgs. Lyngby, Denmark, compute@compute.dtu.dk |
| Series | M.Sc.-2013-96 |
| Note | DTU supervisor: Sven Karlsson, svea@dtu.dk, DTU Compute |
| Electronic version(s) | [pdf] |
| Publication link | http://www.compute.dtu.dk/English.aspx |
| BibTeX data | [bibtex] |
| IMM Group(s) | Computer Science & Engineering |