Mesochronous TDM-based Network-on-Chip | Anders la Cour Bentzon
| | Abstract | Since wire delay makes it difficult to distribute a synchronous clock signal evenly in large digital systems, alternatives to the synchronous design paradigm are called for. This thesis proposes and implements a mesochronous router for a TDM-based network-on-chip. First, a synchronous router is designed, and a bi-synchronous FIFO is then introduced and its use as a synchroniser investigated. These FIFOs are used as synchronisers between the clock domains to make the router mesochronous. Finally, the design is verified to be working in practise as a proof-of-concept on an FPGA.
The solutions mentioned are analysed with regard to area, power consumption and speed, and clock-gated versions of the designs are proposed to reduce power. It is shown that while the mesochronous router works, it is in terms of area almost twice as large as a similar asynchronous router. Thus, the overhead incurred in a mesochronous system seems to favour an asynchronous approach. | | Type | Bachelor thesis [Academic thesis] | | Year | 2012 | | Publisher | Technical University of Denmark, DTU Informatics, E-mail: reception@imm.dtu.dk | | Address | Asmussens Alle, Building 305, DK-2800 Kgs. Lyngby, Denmark | | Series | IMM-B.Sc.-2012-13 | | Note | | | Electronic version(s) | [pdf] | | Publication link | http://www.imm.dtu.dk/English.aspx | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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