Thermal Aware Delay Modelling | Andreas Thor Winther
| | Abstract | Due to large temperature variations in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be di fferent. Traditional thermal aware floorplanning algorithms use wire length to estimate delay and routability. It is shown that using wire length as the evaluation metric does not always produce a floorplan with the shortest delay. A temperature dependent wire delay estimation method for thermal aware floorplanning algorithms which'takes into account the thermal e ffects on wire delay is implemented. In addition, the congestion and reliability issues are discussed as they are closely related to routing and temperature. The MCNC macro block benchmark circuits are used to evaluate the proposed method and the experiment results show that the reduction in wire delay can be quite signi ficant, up to a 20% decrease for the xerox benchmark, with a return cost of 1.01% increased area and 1.02% increased wire length. In ami49, which has the largest number of blocks, the area is increased by 1.01%. Congestion as well as reliability worsen in some cases potentially creating congestion hotspots due to wires being re-routed through colder areas. To address this problem congestion and reliability are added to the evaluation metric thus e ffectively alleviating this problem. | | Type | Master's thesis [Academic thesis] | | Year | 2011 | | Publisher | Technical University of Denmark, DTU Informatics, E-mail: reception@imm.dtu.dk | | Address | Asmussens Alle, Building 305, DK-2800 Kgs. Lyngby, Denmark | | Series | IMM-M.Sc.-2011-73 | | Note | Supervised by Associate Professor Alberto Nannarelli, an@imm.dtu.dk, DTU Informatics | | Electronic version(s) | [pdf] | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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