Translating Communicating Sequential Processes to Formal System Design Models | Fangyi Shi
| | Abstract | This thesis will focus on translating CSP processes to ForSyDe models, before translation, we will introduce some basic operators and typical processes in CSP for which we give translations to ForSyDe. As ForSyDe is a recent system-level model, we will also make a detailed introduction to it. After that, some example based translations will be illustrated to show how CSP processes to be translated to ForSyDe. The CSP processes we considered in this thesis are primitive processes, processes with sending or receiving events, processes with choices (non-deterministic or deterministic choice), and processes containing a recursion. It involves parallelism problems, such as pairwise channel communication and deterministic choice control. Then the construction of CSP processes in ForSyDe will be generalized. Towards channel communication between two processes, we also discuss situations under Advanced Networks rather than Simple Networks. We also propose an alternative approach to translate CSP processes to another low-level model, task graph. Compare with two approaches, we will find the advantage of ForSyDe. All in all, we have achieved our goals but still have some problems left, which will be concluded in the end. | | Type | Master's thesis [Academic thesis] | | Year | 2011 | | Publisher | Technical University of Denmark, DTU Informatics, E-mail: reception@imm.dtu.dk | | Address | Asmussens Alle, Building 305, DK-2800 Kgs. Lyngby, Denmark | | Series | IMM-M.Sc.-2011-50 | | Note | Supervised by Associate Professor Michael R. Hansen, mrh@imm.dtu.dk, DTU Informatics | | Electronic version(s) | [pdf] | | Publication link | http://www.imm.dtu.dk/English.aspx | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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