OCP based adapter for network-on-chip |
| | Abstract | As technology improves, the number of transistors on a single chip is reaching one billion. This allows chip-designers to design complete systems on single chip with multiple CPUs, memory and analog circuits. With the large amount of resources available and with the demand for even shorter development time, reuse of intellectual property (IP) cores becomes inevitable. Today a lot of effort is used to find an easy and efficient way, to let IP cores communicate with each other. A new topology in chip design is network-onchip (NoC). With NoC the communication between cores can be standardized and traditional ad-hoc and/or bus-based solutions can be replaced with an on-chip network.
This thesis presents two network adapters for an asynchronous on-chip network. Our network adapters decouple communication from computation through a shared memory abstraction. We use Open Core Protocol (OCP) to provide a standard socket interface for connecting IP cores. The network adapters provide guaranteed services via connections and connection-less best effort services via source routing. The implementation of our network adapters has an area of 0.18mm2 and 0.13mm2 using a 0.18μm technology, and they run at a frequency of 225MHz. A proposal for the improvement of synchronization between the synchronous and asynchronous domains is elaborated in this report, as studies have shown that the existing synchronization mechanism limits the throughput of the transactions and increases their latency. | | Type | Master's thesis [Academic thesis] | | Year | 2005 | | Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU | | Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby | | Series | IMM-Thesis-2005-15 | | Note | | | Electronic version(s) | [pdf] | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
|