System Level Platform Modeling for System-on-Chip | David Ritter
| | Abstract | SoC design using IP-based design methodologies allows a large degree of design flexibility. Designers may wish to use design space exploration techniques to find optimal SoC designs for a given application. To do so, however, fast and accurate estimation of each design s performance is needed. In this project, SoC performance estimation techniques are explored, focusing on processor-based platforms. A flexible methodology, the SoC Platform Architecture Model (SPAM), is developed for specifying platform configurations, component properties, and workload properties. A set of performance models for processors, bus interconnect, and shared or private memories is presented. These models are then combined using the SPAM methodology, and applied to modeling of a variety of single processor and multiprocessor SoC platforms. The potential for extension of the SPAM modeling system is also explored. | | Type | Master's thesis [Academic thesis] | | Year | 2004 | | Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU | | Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby | | Series | IMM-Thesis-2004-66 | | Note | Supervised by Prof. Jan Madsen | | Electronic version(s) | [pdf] | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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