@MASTERSTHESIS\{IMM2004-03284,
    author       = "D. Ritter",
    title        = "System Level Platform Modeling for System-on-Chip",
    year         = "2004",
    school       = "Informatics and Mathematical Modelling, Technical University of Denmark, {DTU}",
    address      = "Richard Petersens Plads, Building 321, {DK-}2800 Kgs. Lyngby",
    type         = "",
    note         = "Supervised by Prof. Jan Madsen",
    url          = "http://www2.compute.dtu.dk/pubdb/pubs/3284-full.html",
    abstract     = "SoC design using {IP-}based design methodologies allows a large degree of design flexibility. Designers may wish to use design space exploration techniques to find optimal SoC designs for a given application. To do so, however, fast and accurate estimation of each design s performance is needed. In this project, SoC performance estimation techniques are explored, focusing on processor-based platforms. A flexible methodology, the SoC Platform Architecture Model (SPAM), is developed for specifying platform configurations, component properties, and workload properties. A set of performance models for processors, bus interconnect, and shared or private memories is presented. These models are then combined using the {SPAM} methodology, and applied to modeling of a variety of single processor and multiprocessor SoC platforms. The potential for extension of the {SPAM} modeling system is also explored."
}