Architectural aspects of design for low static power consumption |
Martin Hans
|
| Abstract | In the presence of non-negligible leakage power, the way to design architectures for low power consumption may have changed. This master's thesis represents one step towards exploring low power design again. This thesis shows, that area is not a sufficient predictor of leakage power consumption when delay requirements are tight.
Architectural voltage scaling is re-evaluated and it is shown that it does not always reduce leakage power. Opportunities for reducing the leakage associated with repeaters used in long on-chip wires are explored.
Furthermore, a novel architecture level power estimation method is presented which allows the designer to explore design space early in the design process. |
| Keywords | leakage power, static power, total power, architecture, high level power estimation, architectural voltage scaling, repeater leakage |
| Type | Master's thesis [Academic thesis] |
| Year | 2004 |
| Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU |
| Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby |
| Series | IMM-Thesis-2004-64 |
| Note | Supervised by Flemming Stassen |
| Electronic version(s) | [pdf] [zip] |
| BibTeX data | [bibtex] |
| IMM Group(s) | Computer Science & Engineering |