Simulation based sequential circuit automated test pattern generation |
Jing Yuan
|
| Abstract | The aim with this paper is to design a high e cient sequential ATPG on single stack-at fault model.A new approach for sequential circuit test generation is proposed in this paper.With combining the advantage of logic simulation based ATPG and fault simulation based ATPG, higher fault coverage and shorter test sequential length are achieved for benchmark circuit instead of pure logic or fault simulation based ATPG.
A new high e cient fault simulation algorithm which is based on PROOFs [39 ]is presented. Here two new techniques are used to accelerate parallel fault simulation:1) X algorithm preprocessing, 2) Dynamic fault ordering method. Based on experiment result,these two heuristic accelerate fault simulation by 1.2 time in fault simulation.
Two metaheuristic algorithms,genetic algorithm and Tabu search,are investigated in test generation process.These algorithms are used to generate population of candidate test vectors and optimize vectors. |
| Type | Master's thesis [Academic thesis] |
| Year | 2004 |
| Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU |
| Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby |
| Series | IMM-Thesis-2004-58 |
| Note | Supervised by Assoc. Prof. Flemming Stassen |
| Electronic version(s) | [pdf] [ps] |
| BibTeX data | [bibtex] |
| IMM Group(s) | Computer Science & Engineering |