Design of CMOS cell libraries for minimal leakage currents |
Jacob Gregers Hansen
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| Abstract | Leakage due to scaling down CMOS device sizes will be the major power consumption source in cell based IC design in a few years. This work addresses the problem of this leakage, investigating the possibilities of utilizing alternative logic families instead of static CMOS for the creation of a low leakage cell library. For this purpose, MTCMOS, CPL and Domino logic are investigated for leakage characteristics and are found unusable for low leakage design.
Using cell libraries of small logic cells for IC design is found to be the major reason for much of the leakage. Synthesizing without cell boundaries by building larger cells reduces the leakage problem greatly. A new synthesis flow and cell library is proposed. |
| Keywords | Low leakage CMOS, CPL, Domino, MTCMOS, MacroCMOS, Synthesis for low leakage design. |
| Type | Master's thesis [Academic thesis] |
| Year | 2004 |
| Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU |
| Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby |
| Series | IMM-Thesis-2004-55 |
| Note | Supervised by Assoc. Prof. Flemming Stassen |
| Electronic version(s) | [pdf] [ps] |
| BibTeX data | [bibtex] |
| IMM Group(s) | Computer Science & Engineering |