Asynchronous implementation of virtual channels in on-chip networks |
| | Abstract | On-chip network has been proposed as a method to overcome two major challenges in future SoC designs: The challenge of increasing design-effort needed to implement reliable inter-module communication in SoCs, and the projected bottleneck in non-scalable global wires.
Several proposals for NoC designs have already been proposed, but mostly using synchronous approaches. This thesis investigates design of on-chip network links using asynchronous circuits, and presents three link designs of which two are providing virtual channels. The link designs have been implemented using customizable macros, which are generating link instances as verilog standard cell netlists. Link instances have been simulated with back-annotated pre-layout timing estimations for a 0.18um CMOS technology. The implementations are evaluated on performance and cost to identify the trade-offs present when choosing between the designs, and to determine the penalty for increasing the number of channels on the link. | | Keywords | System-on-Chip, Nework-on-Chip, Virtual-Channals, Asynchronous Design | | Type | Master's thesis [Academic thesis] | | Year | 2004 | | Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU | | Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby | | Series | IMM-thesis-2004-25 | | Note | | | Electronic version(s) | [pdf] [ps] | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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