Lectures 10 through 12:
CMOS system design
Lecture 10:
Clock distribution and interconnect
- Purpose:
Design issues of the chip infrastructure
- Contents:
- Packaging
Power distribution
Clock distribution
- Literature:
- Weste & Harris chapters 4 and 12
Lecture 11:
Data path and memory subsystems
- Purpose:
How to design datapaths and memories for low lower
- Contents:
-
Data path design
Memory design
- Literature:
- Weste & Harris chapters 10 - 11
Lecture 12:
Testing and verification
- Purpose:
How to verify the bahaviour of CMOS circuits
- Contents:
- Fault modeling: stuck-at faults
Test pattern generation: D-algorithm
Testing: IDDQ-test and delay test
Verification
Design for test: scan path design
Boundary scan design and Built-In Self Test
- Literature:
- Weste & Harris chapter 9
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Associate professor Flemming Stassen,
stassen@imm.dtu.dk