Exercises

Demo: CMOS Power Consumption

CMOS logic has (almost) no static power dissipation. If the gate voltage is either '1' or '0', there is no conducting path from VDD to GND, i.e. there is no static current path through the inverter. A short-circuit condition arises only when the gate voltage is switched, typically during a short interval in time. Typical switching times are 1 ns or less. During this interval, a short-circuit power dissipation occurs. However, there is a significant dynamic power dissipation in CMOS gates. The applet below illustrates this effect for the CMOS inverter.

The gate of a MOS transistor forms a small capacitor, Cgs. Typical values for the gate capacitance is Cgs = 5 fF. If the inverter input is connected to VDD at time t1, this capacitor is charged:

Qgs = Cgs * VDD
If the input is connected to GND at time t2, the capacitor is discharged. The net effect of this is a current of
I = dQ/dt = (Cgs * VDD)/(t2-t1)

The later is called dynamic power consumption. Though the contribution seems small, the total current drawn by the entire CMOS chip can be quite large:

The applet illustrates the current dissipation in the CMOS inverter. If the input voltage stays at '1' or '0', either the N-type or the P-type transistor in nonconducting, and no current flows through the inverter.
When the input is switched, the gates of the transistors are charged/discharged. The applet draws a moving electron to illustrate this. During the switching, the input voltage passes the region close to VDD/2, i.e. a short-circuit current flows through the inverter. This current again is shown by a moving electron.

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Top of demo         Modified by Flemming Stassen on 26 August 1999     stassen@imm.dtu.dk