The following three applets illustrate complementary MOS logic.

CMOS technology is inherently complementary, i.e. P-type transistors are connected in series (parallel) between V_DD and and the output Y, while the N-type transistors are connected in parallel (series) between GND and the output Y. That is, the N-type and the P-type networks are complementary with respect to topology.

Furthermore, inputs at '0' can create a conducting path from V_DD to the output (output level '1'), whereas inputs at '1' blocks the path between V_DD and the output while opening a path from GND to the output (so that the output level is '0'). The voltage levels are inverted.

The following three applets demonstrate the 2-input NAND, the 2-input NOR and the 3-input NAND gates:

• Click the mouse near the inputs to toggle the input voltages and watch the resulting output voltage.
• The corresponding combination of input and output values is hightlighted in the function-table on the right.
• Click on a function-table entry to select the corresponding input voltages.
• Clicking on the top line of the function-table will step through the function-table.

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Top of demo         Modified by Flemming Stassen on 26 August 1999     stassen@imm.dtu.dk

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