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The ARTS website is of interest to all of you who want a system-level framework to model networked multi-processor systems-on-chip (MPSoC) and evaluate the crosslayer causality between the application, the operating system (OS) and the platform architecture.

Publications

Conference and book chapters in reverse chronological order:

Mahadevan, S., Storgaard. M., and Madsen, J. “ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality.” 13th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Atlanta USA. IEEE, Sept. 2005: 480-483. [Bibtex]

Madsen, J., Mahadevan, S., and Virk, K. “Chapter 13: Network-Centric System-Level Model for Multiprocessor System-on-Chip Simulation.” Interconnect-Centric Design for Advanced SoC and NoC. Eds. Nurmi J., Tenhunen H., Isoaho J., and Jantsch A. Dordrecht. Kluwer Publications, The Netherlands, 2004: 341-365. [Bibtex]

Virk, K., Madsen, J., “A system-level multiprocessor system-on-chip modelling framework.” International Symposium on System-on-Chip (ISSoC), Tampere, Finland. Nov. 2004. [Bibtex]

Madsen, J., Virk, K., Gonzalez, M. J., “A SystemC-Based Abstract Real-Time Operating System Model for Multiprocessor System-on-Chip.” Multiprocessor System-on-Chip. Eds. Jerray A., and Wolf W. Morgan Kaufmann, 2004. [Bibtex]

Madsen, J., Mahadevan, S., and Virk, K. and Gonzalez, M. “Network-on-Chip Modeling for System-Level Multiprocessor Simulation.” In Proceedings of the 24th Real-Time Systems Symposium (RTSS), Cancun Mexico. IEEE, Dec. 2003: 265-274. [Bibtex]

Virk, K., Madsen, J., “Resource Allocation Model for Modelling Abstract RTOS on Multiprocessor System-on-Chip.” The 21th Norchip Conference (NorChip), Tampere, Finland. 2003: 48-51. [Bibtex]

Madsen, J., Virk, K., Gonzalez, M. J., “Abstract RTOS Modelling for Multiprocessor System-on-Chip.” International Symposium on System-on-Chip (ISSoC), Tampere, Finland. 2003: 147-150. [Bibtex]