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| Bachelorprojekt - Softwareteknologi | Project No. 0183: RISC-V Pipeline Simulator |
| Aktuelle | Tidligere |
We intend to use RISC-V in the future for teaching Computer Architecture Engineering. For this we need a pipeline simulator of RISC-V. The pipeline simulator shall provide a standard 5-stage pipeline that executes RISC-V base instructions and show graphically what instructions are doing in each stage. As a start we provide a instruction set simulator of RISC-V (about 200 lines of code).
| Prerequisites: | 02155 Computer Architecture and Engineering (recommended) |
Supervisor(s) Martin Schöberl
| Sidst opdateret: Nov 18, 2016 af Hans Henrik Løvengreen |