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| Bachelorprojekt - Softwareteknologi | Projekt nr. 0026: |
| Aktuelle | Tidligere |
The project is related to a research project on synthesis and optimization of clockless circuits. State-of-the-art clockless hardware synthesis systems translates a system of communicating processes described in a CSP like programming language (you may know this from course 02152) into a hardware implementation.
In order to add automatic optimization to the synthesis process, it is necessary translate the program text into a corresponding control data flow graph (CDFG), which is the internal representation used in the optimization tool.
The goal of the project is to develop such a front-end which can parse a subset of the input language and create a CDFG-representation. The specific input language is called Haste (see www.handshakesolutions.com) and we will limit the scope to a single process whose body consists of a sequence of simple loops and assignment statements.
(The project can be extended to accommodate a group of two students.)
Vejleder(e): Jens Sparsø, Christian W. Probst
| Sidst opdateret: Oct 31, 2011 af Hans Henrik Løvengreen |