AVR Core

The AVR_Core project from OpenCores.org has been translated from VHDL to SystemC. AVR is an 8-bit RISC architecture from ATMEL. The core executes all AVR instructions. Extra low-power logic has been added to support sleep and halt modes. The AVR core should be synthesizable, but there are problems with several jump instructions after synthesis. These are caused by strange problems with initialization of the program counter.

Developers: Ruslan Lepetenok (originator) & Nicolai Ascanius Jørgensen (SystemC translation).
Download: sc_avr_core.tar.gz

Setup of core

In order to execute the core, SystemC has to been installed. The SystemC distribution can be downloaded from systemc.org
SystemC requires GCC for the local platform. When compiling test programs or TinyOS for AVR, a GCC distribution for the AVR architecture is required.

TinyOS can be downloaded from the TinyOS homepage. The distribution requires GCC for AVR to compile.

Other download locations

Zipped GCC distribution for AVR: Download file
Zipped TinyOS distribution for AVR: Download file
Zipped GTKWave distribution: Download here

Test programs

The AVR core have been tested with a set of test programs compiled from C to assembly code with GCC. The programs test various things which should be self-explanatory from the name of the program or just by taking a glance at the code.

Download: test_programs_avr.tar.gz