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I am currently a firmware developer at Oticon. From May 2013 to May 2016, I was a postdoc researcher at DTU Compute in Copenhagen, Denmark, working in the RTEMP project. From May 2012 to May 2013, I was a postdoc researcher at the DTIM group of ONERA in Toulouse, France, in the scope of the TOAST project. Before that, since January 2008, I worked as research and teaching assistant at the Institute of Computer Engineering at the Vienna University of Technology in Vienna, Austria, where I defended my PhD thesis in March 2012.
My research interests span a range of topics in the area of real-time embedded systems. The topic of my PhD thesis was hard real-time garbage collection on chip multi-processors. My current research is focused on time-predictable computer architectures, combining the areas of hardware design and worst-case execution time analysis. Furthermore, I am interested in predictable execution of real-time systems on many-core architectures.
JEOPARD Java environment for parallel realtime development
TOAST Time-oriented critical systems, part of the «chantier» TORRENTS (Time oriented reliable embedded networked systems)
T-CREST Time-predictable multi-core architecture for embedded systems
RTEMP Hard real-time embedded multiprocessor platform
JOP The Java-Optimized Processor.
Lemberg My personal time-predictable VLIW processor.
Patmos The time-predictable VLIW processor of the T-CREST and RTEMP projects.
Prelude A multi-rate synchronous language.
SchedMCore A real-time scheduling framework.
A complete list of my publications can be found here. Reasonably complete publication lists can also be found at Google Scholar or DBLP.
execution time analysis of dynamic branch prediction
Proceedings of the 28th Euromicro Conference on Real-Time Systems, ECRTS '16, Toulouse, France, 152--162. IEEE, 2016
multiplexing vs network calculus: A comparison
Wolfgang Puffitsch, Rasmus Bo Sørensen, Martin Schoeberl
Proceedings of the 23rd International Conference on Real-Time Networks and Systems, RTNS '15, Lille, France, 289--296. ACM, 2015
Off-line mapping of
multi-rate dependent task sets to many-core platforms
Wolfgang Puffitsch, Eric Noulard, Claire Pagetti
Real-Time Systems, 51(5): 526--565, 2015
Time-predictable multi-core architecture for embedded systems
Martin Schoeberl, Sahar Abbaspour, Benny Akesson, Neil Audsley, Raffaele Capasso, Jamie Garside, Kees Goossens, Sven Goossens, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber, Alexander Jordan, Evangelia Kasapaki, Jens Knoop, Yonghui Li, Daniel Prokesch, Wolfgang Puffitsch, Peter Puschner, André Rocha, Cláudio Silva, Jens Sparsø, Alessandro Tocchi
Journal of Systems Architecture, 61(9): 449--471, 2015
Design and analysis of a hard
real-time garbage collector for a Java chip multi-processor
Concurrency and Computation: Practice and Experience, 25(16): 2269--2289, 2013
Time-Predictability on Multi-/Many-Core Platforms
presented at CESEC Summer School 2015, Toulouse, France
Program chair for JTRES 2014.
Member of the program committee for JTRES 2012, 2013, 2015, and 2016; MARC 2012; ISORC 2015 and 2016; RTN 2016; WCET 2016.
Reviewer for Software: Practice and Experience, Journal of Systems Architecture, Computer, Transactions on Software Engineering, Leibniz Transactions on Embedded Systems, Concurrency and Computation: Practice and Experience (special issue: JTRES 2009), Advances in Computers (special issue: Data Flow versus Control Flow: Creativity, Design, Application, and Education).
Secondary reviewer for DATE'11, DATE'12, ECRTS'10, ECRTS'11, FPL'14, FPL'15, HiRES'15, ISORC'14, PPPJ'14, RTAS'10, RTSS'09, RTSS'11, SAC'13, SAC'15, WCET'15, Transactions on Industrial Informatics.
In 2014 and 2015, I gave lectures for the courses Advanced Computer Architecture and Computer Architecture and Engineering at DTU.
In spring 2013, I assisted in the tutorials for the course Engineering of Protocols at ENSEEIHT in Toulouse.
In the winter semester 2011, I taught the mandatory bachelor level lab course Digital Design and Computer Architecture at the TU Vienna, being responsible for the computer architecture part, where students implement a MIPS-compatible processor.
In 2009 and 2010, I taught the elective lab course Computer Architecture at the TU Vienna, where master students designed and implemented their own pipelined processor. I also supervised the lab course Electrical Engineering for Computer Engineers.
During my studies, I was tutor for several courses, including the lab courses “Microcontroller”, “Systems Programming” and “Embedded Systems Programming”.