| [1] |
J. Sparsø, T. Bolander, P. Fischer, T.K. Hansen, . Høgh, M. Nyborg, C.W.
Probst, and E.A. Todirica.
CDIO Projects in DTU’s B.Eng. in IT Study Program.
In Proceedings of the 7th International CDIO Conference,
pages 1-12. Technical University of Denmark, June 2011. |
| [2] |
M. B. Stuart, M. B. Stensgaard, and J. Sparsø.
The ReNoC reconfigurable network-on-chip: Architecture,
configuration algorithms, and evaluation.
ACM Transactions on Embedded Computing Systems,
10(4):45:1-45:26, 2011. |
| [3] |
M. B. Stuart and J. Sparsø.
Analytical derivation of traffic patterns in cache-coherent
shared-memory systems.
Microprocessors and Microsystems (Elsevier), 35(7):632-642,
2011. |
| [4] |
O. C. Akgun, J. N. Rodrigues, and J. Sparsø.
Minimum energy sub-threshold self-timed circuits using current
sensing completion detection.
IET Computers & Digital Techniques, 5(4):342-353, 2011. |
| [5] |
O. C. Akgun, J. N. Rodrigues, and J. Sparsø.
Minimum-Energy Sub-Threshold Self-Timed Circuits: Design Methodology
and a Case Study.
In Proc. International Symposium on Asynchronous Circuits and
Systems, pages 41-51. IEEE Computer Society Press, 2010. |
| [6] |
M. S. Rasmussen, S. Karlsson, and J. Sparsø.
Performance Analysis of a Hardware/Software-Based Cache Coherency
Protocol in Shared Memory MPSoCs.
In Workshop on Programming models for Emerging Architectures
(PMEA), Raleigh, North Carolina, September 2009. |
| [7] |
M. E. Vigild, L. E. Willumsen, E. Borchersen, K. Clement, L. B. Jensen,
C. Kjærgaard, P. Klit, and J. Sparsø.
Comparison and Classification of Design-Build Projects in Different
Engineering Bachelor Programs.
In Proceedings of the 5th International CDIO Conference.
Singapore Polytechnic, June 2009. |
| [8] |
S. F. Nielsen, J. Sparsø, and J. Madsen.
High-level synthesis of asynchronous circuits using syntax directed
translation as backend.
IEEE Transactions on VLSI Systems, 17(2):248-261, 2009. |
| [9] |
S. F. Nielsen, J. Sparsø, J.B. Jensen, and J.S.R. Nielsen.
A Behavioral Synthesis Frontend to the Haste/TiDE design flow.
In Proc. International Symposium on Asynchronous Circuits and
Systems, pages 185-194. IEEE Computer Society Press, 2009.
(Best paper finalist). |
| [10] |
J. Sparsø.
Current Trends in High-Level Synthesis of Asynchronous Circuits.
In IEEE International Conference on Electronics Circuits and
Systems (ICECS), pages 347-350, 2009. |
| [11] |
M. B. Stuart, M. B. Stensgaard, and J. Sparsø.
Synthesis of Topology Configurations and Deadlock Free Routing
Algorithms for ReNoC-based Systems-on-Chip.
In Proc. Embedded Systems Week 2009 - 7th IEEE/ACM
International Conference on Hardware/Software Codesign and System Synthesis
(CODES+ISSS), pages 481-490, 2009. |
| [12] |
M. B. Stuart and J. Sparsø.
Analytical Derivation of Traffic Patterns in Shared Memory
Architectures from Task Graphs.
In Proc. 27th IEEE Norchip Conference, pages 1-4. IEEE
Computer Society Press, 2009. |
| [13] |
M. S. Rasmussen, S. Karlsson, and J. Sparsø.
Adaptable Support for Programming Models in Many-core
Architectures.
In Workshop on New Directions in Computer Architecture, 2009. |
| [14] |
M. May, L. Sendrup, J. Sparsø, and T. K. Johansen.
E-learning support for student's understanding of electronics.
In Proceedings of the 4th International CDIO Conference.
Ghent, June 2008. |
| [15] |
Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, and Jan
Madsen.
A Reactive and Cycle-True IP Emulator for MPSoC Exploration.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 27(1):109-122, January 2008. |
| [16] |
S. Mahadevan, F. Angiolini, R. G. Olsen, J. Sparsø, and J. Madsen.
A network traffic generator model for fast network-on-chip
simulation.
In R. Lauwereins and J. Madsen, editors, Design, Automation,
and Test in Europe: The Most Influential Papers of 10 Years DATE, pages
173-184. Springer, 2008. |
| [17] |
M. B. Stensgaard and J. Sparsø.
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology.
In Proc. 2nd IEEE International Symposium on Networks-on-Chip,
pages 55-64. IEEE Computer Society Press, 2008. |
| [18] |
J. Sparsø, P. Klit, M. May, G. Mohr, and M. E. Vigild.
Towards CDIO-based B.Eng. studies at the Technical University of
Denmark.
In Proceedings of the 3rd International CDIO Conference,
pages 1-11. Massachusetts Institute of Technology, June 2007. [ .pdf ] |
| [19] |
T. Bjerregaard, M.B. Stensgaard, and J. Sparsø.
A scalable, timing-safe, network-on-chip architecture with an
integrated clock distribution method.
In Proc. Design Automation and Test in Europe (DATE), pages
648-653. IEEE Computer Society Press, 2007. |
| [20] |
Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, and Jan
Madsen.
A traffic injection methodology with support for system-level
synchronization.
In R. Reis, A. Osseiran, and H.-J. Pfleiderer, editors,
VLSI-SoC: From Systems to Silicon, IFIP series, pages 145-161. Springer,
2007.
(Extended and revised best papers from IFIP TC 10, WG 10.5,
Thirteenth International Conference on Very Large Scale Integration of System
on Chip (VLSI-SoC), 2005). |
| [21] |
J. Sparsø.
Asynchronous design of Networks-on-Chip (Invited presentation).
In Proc. 25th IEEE Norchip Conference, pages 1-4. IEEE,
2007. |
| [22] |
M. B. Stuart and J. Sparsø.
Custom Topology Generation for Network-on-Chip.
In Proc. 25th IEEE Norchip Conference, pages 1-4. IEEE,
2007. |
| [23] |
G. Mohr et al.
CDIO på DTU's diplomingeniøruddannelser - Handlingsplan
2007-2008.
Technical report, Technical University of Denmark, 2007.
Note: Report written by the Dean's CDIO task force. Describies the
plan of action for introcucing CDIO (Concieve Design Implement Operate, see
www.cdio.org) as the basis for all of DTU's 8 B. Eng. study programs. |
| [24] |
Jens Sparsø and Alexander Yakovlev, editors.
Proceedings of ASYNC'2006 - 12th IEEE Intl. symposium on
asynchronous circuits and systems. IEEE Computer Society Press, October
2006.
440 pages. |
| [25] |
T. Bjerregaard and J. Sparsø.
Implementation of Guaranteed Services in the MANGO Clockless
Network-on-Chip.
IEE Proceedings: Computing and Digital Techniques,
153(4):217-229, 2006. |
| [26] |
T. Bjerregaard and J. Sparsø.
Packetizing OCP Transactions in the MANGO Network-on-Chip.
In 9th EUROMICRO Conference on Digital System Design (DSD'06),
pages pp. 657-664. IEEE Computer Society Press, 2006. |
| [27] |
M. B. Stensgaard, T. Bjerregaard, J. Sparsø, and J. H. Pedersen.
A simple clockless Network-on-Chip for a commercial audio DSP chip.
In 9th EUROMICRO Conference on Digital System Design (DSD'06),
pages pp. 641-648. IEEE Computer Society Press, 2006. |
| [28] |
T. Bjerregaard, S. Mahadevan, R. G. Olsen, and J. Sparsø.
An OCP compliant network adapter for GALS-based SoC design
using the MANGO network-on-chip.
In Proceedings of the International Symposium on System-on-Chip
(SoC'05), pages 171-174. IEEE, November 2005. |
| [29] |
F. Angiolini, S. Mahadevan, J. Madsen, L. Benini, and J. Sparsø.
Realistically rendering SoC traffic patterns with interrupt
awareness.
In IFIP International Conference on Very Large Scale
Integration (VLSI-SoC 2005), pages 211-216, September 2005. |
| [30] |
T. Bjerregaard and J. Sparsø.
A Router Architecture for Connection-Oriented Service Guarantees in
the MANGO Clockless Network-on-Chip.
In Proc. Design Automation and Test in Europe (DATE), pages
1226-1231. IEEE Computer Society Press, 2005. |
| [31] |
T. Bjerregaard and J. Sparsø.
A Scheduling Discipline for Latency and Bandwidth Guarantees in
Asynchronous Network-on-chip.
In Proc. International Symposium on Asynchronous Circuits and
Systems, pages 34-43. IEEE Computer Society Press, 2005.
(Best paper award). |
| [32] |
T. Bjerregaard, J. Sparsø, S. Mahadevan, and J. Madsen.
Modular SoC-Design using the MANGO clockless NoC.
In International Conference on Parallel Computing (PARCO'05),
2005.
(Invited presentation). |
| [33] |
S. Mahadevan, M. Storgaard, R. Olsen, J. Sparsø, J. Madsen, and
F. Angiolini.
A Network Traffic Generator Model for Fast Network-on-Chip
Simulation.
In Proc. Design Automation and Test in Europe (DATE), pages
780-785. IEEE Computer Society Press, 2005. |
| [34] |
Ö. Paker, J. Sparsø, M. Isager, N. Haandbæk, and L. S. Nielsen.
A heterogenous low-power multiprocessor architecture for audio signal
processing.
Journal of VLSI Signal Processing, 37(1):89-106, 2004. |
| [35] |
J. Sparsø.
Future networks-on-chip; will they be synchronous or asynchronous?
(invited talk).
In SSoCC'04 (Swedish System on Chip Conference, Båstad),
page 2 pages, 2004. |
| [36] |
S. F. Nielsen, J. Sparsø, and J. Madsen.
Towards behavioral synthesis of asynchronous circuits - an
implementation template targeting syntax directed compilation.
In Proceedings of the Euromicro Symposium on Digital System
Design, pages 298-305. IEEE Computer Society Press, 2004. |
| [37] |
T. Bjerregaard and J. Sparsø.
Virtual channel designs for guaranteeing bandwith in asynchronous
network-on-chip.
In 22nd Norchip Conference, pages 269-272. IEEE, 2004. |
| [38] |
T. Bjerregaard, S. Mahadevan, and J. Sparsø.
A channel library for asynchronous circuit design supporting
mixed-mode modelling.
In Odysseas Koufopavlou Enrico Macii, Vassilis Paliouras, editor,
PATMOS 2004 (14th Intl. Workshop on Power and Timing Modeling,
Optimization and Simulation), Lecture Notes in Computer Science, LNCS3254,
pages 301-310. Springer, 2004. |
| [39] |
N. Streltsov, J. Sparsø, S. Bokov, and S. Kleberg.
The Synputer - a novel MIMD processor targeting high performance
low power DSP applications.
In International Signal Processing Conference 2003, pages
CD-ROM. Global Technology Conferences ( www.gt-conferences.com ), April
2003. |
| [40] |
J. Sparsø.
The Thomas B. Thrige center for Microinstruments, Report 1999-2002.
Technical report, Technical University of Denmark, 2003.
Available on line at http://www.imm.dtu.dk/ ˜jsp/cfm/TBTCfMreport.pdf. |
| [41] |
S. Mahadevan, T. Bjerregaard, J. Sparsø, and J. Madsen.
Using SystemC to model asynchronous communication at different
levels of abstraction.
In Third ACiD-WG Workshop (of the European Commission's fifth
Framework Programme), 2003. |
| [42] |
Ö. Paker, J. Sparsø, N. Haandbæk, M. Isager, and L. S. Nielsen.
A heterogenous multi-core platform for low power signal processing.
In Proc. of ESSCIRC 2002, 28th IEEE European Solid-State
Circuits Conference, pages 73-76, September 2002. |
| [43] |
V. Oklobdzija and J. Sparsø.
Embedded tutorial 1: Future Directions in Clocking Multi-GHz
Systems.
In Proc. of ISLPED'02 (International Symposium on Low Power
Electronics and Design), page 219, August 2002. |
| [44] |
Ö. Paker and J. Sparsø.
A heterogenous multi-core platform for low power signal processing in
systems-on-chip.
In Workshop on Heterogenous Reconfigurable Systems on Chip
(SoC). RWTH Aachen, April 2002. |
| [45] |
S. F. Nielsen, J. Sparsø, J. Madsen, J. Hammerstoft, and J. S. Hansen.
High-level synthesis of asynchronous circuits from control data flow
graph representations.
In Second ACiD-WG Workshop (of the European Commission's fifth
Framework Programme), January 2002. |
| [46] |
S. F. Nielsen and J. Sparsø.
Analysis of low-power SoC interconnection networks.
In IEEE 19th Norchip Conference, pages 77-86. IEEE, December
2001. |
| [47] |
Ö. Paker, J. Sparsø, N. Haandbæk, M. Isager, and S. S. Nielsen.
A heterogenous multiprocessor architecture for low-power audio signal
processing.
In A. Smailagic and H. De Man, editors, VLSI'2001, IEEE Computer
Society Workshop on VLSI, pages 47-53. IEEE Computer Society Press, April
2001. |
| [48] |
J. Sparsø and S. Furber, editors.
Principles of asynchronous circuit design - A systems
perspective.
Kluwer Academic Publishers, 2001. |
| [49] |
J. Sparsø.
Asynchronous circuit design - a tutorial.
In J. Sparsø and S. Furber, editors, Principles of
asynchronous circuit design - A systems perspective, chapter 1-8, pages
1-152. Kluwer Academic Publishers, 2001. |
| [50] |
S. Frankild and J. Sparsø.
Channel Abstraction and Statement Level Concurrency in VHDL++.
In 4th Asynchronous Circuit Design Workshop - ACiD 2000.
National Polytechnic Institute of Grenoble, TIMA, 2000. |
| [51] |
Jens Sparsø and Dimitrios Soudris, editors.
Proceedings of PATMOS'99, 9th Int. Workshop on Power and Timing
Modeling, Optimization and Simulation. Democritus University of Thrace,
Greece, October 1999.
398 pages. |
| [52] |
Lars S. Nielsen and Jens Sparsø.
Designing asynchronous circuits for low power: An IFIR filter bank
for a digital hearing aid.
Proceedings of the IEEE, 87(2):268-281, February 1999. |
| [53] |
M. Pedersen and J. Sparsø.
Asynchronous Design using plain VHDL in a standard CAD-tool
framework.
In 3rd Asynchronous Circuit Design Workshop - ACiD-WG.
Newcastle upon Tyne, U.K., 1999.
CS-TR-670, TR Series, Dept. of CS, Univ. Newcastle. |
| [54] |
Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors.
Proceedings of PATMOS'98, 8th Int. Workshop on Power and Timing
Modeling, Optimization and Simulation. Technical University of Denmark,
October 1998.
440 pages. |
| [55] |
Jens Sparsø.
Lavenergi kredsløb.
Naturens Verden, (9):355-364, September 1998. |
| [56] |
E. Paaske, J. Justesen, K. Larsen, Flemming Hansen, S. Pedersen, J. Sparsø,
J. D. Andersen, T. B. Bach, and T. F. Garde.
High Speed Frame Synchronization and Viterbi Decoding.
European Space Agency Contract Report TELE-12-ISSN 1396-1535,
Technical University of Denmark, March 1998.
301 pages. |
| [57] |
Lars S. Nielsen and Jens Sparsø.
An 85 μ W Asynchronous Filter-Bank for a Digital Hearing Aid.
In Proc. IEEE International Solid State circuits Conference,
pages 108-109, 1998. |
| [58] |
K. T. Christensen, P. Jensen, P. Korger, and J. Sparsø.
The Design of an Asynchronous TinyRISC TR4101 Microprocessor Core.
In Proc. International Symposium on Asynchronous Circuits and
Systems, pages 108-119. IEEE Computer Society Press, 1998. |
| [59] |
J. Sparsø (editor).
Summer School on Asynchronous Circuit Design, August 18-22, 1997.
Technical report, Technical University of Denmark, 1997. |
| [60] |
Lars S. Nielsen and Jens Sparsø.
A Low-power Asynchronous Data-path for a FIR Filter Bank.
In Proc. International Symposium on Asynchronous Circuits and
Systems, pages 197-207. IEEE Computer Society Press, 1996. |
| [61] |
Jens Sparsø, Jørgen Staunstrup, and Mark B. Josephs (editors).
ACiD-WG workshop on asynchronous low-power VLSI, Lyngby,
Denmark, April 11-12.
Technical Report ID-TR:1994-140, Department of Computer
Science, Technical University of Denmark, June 1994. |
| [62] |
J. Sparsø.
Studievejledning 1994.
Technical Report ID-U/1994-66, Technical University of Denmark,
1994.
19 pages. |
| [63] |
J. Sparsø.
Temporale forhold i synkrone integrerede kredsløb med 2-fase klok.
Technical Report ID-U/1994-69, Department of Computer Science,
Technical University of Denmark, 1994.
19 pages. |
| [64] |
Lars S. Nielsen and Jens Sparsø.
Low-power operation using self-timed circuits and adaptive scaling
of the supply voltage.
In 1994 IEEE International Workshop on Low Power
Design, Napa, CA, April 22-27, pages 99-104, 1994. |
| [65] |
L. S. Nielsen, C. Niessen, J. Sparsø, and C. H. van Berkel.
Low-power operation using self-timed circuits and adaptive scaling
of the supply voltage.
IEEE Transactions on VLSI Systems, 2(4):391-397, 1994. |
| [66] |
Jens Sparsø and Jørgen Staunstrup.
Delay-insensitive multi-ring structures.
INTEGRATION, the VLSI Journal, 15(3):313-340, October
1993. |
| [67] |
J. Sparsø and J. Staunstrup.
Design and performance analysis of delay insensitive multi-ring
structures.
In T. N. Mudge, V. Milutinovic, and L. Hunter, editors, Proc. of
HICSS-26, Hawaii International Conference on Systems Sciences, January 5-8,
1993, Volume 1: Architecture, pages 349-358. IEEE Computer Society Press,
January 1993. |
| [68] |
Jens Sparsø, Christian D. Nielsen, Lars S. Nielsen, and Jørgen
Staunstrup.
Design of self-timed multipliers: A comparison.
In S. Furber and M. Edwards, editors, Asynchronous Design
Methodologies, volume A-28 of IFIP Transactions, pages 165-180.
Elsevier Science Publishers, 1993. |
| [69] |
Jens Sparsø and Jørgen Staunstrup.
Design and performance analysis of delay-insensitive multi-ring
structures.
Technical report, Department of Computer Science, Technical
University of Denmark, December 1992.
pages 1-25. |
| [70] |
F. Bauduin, R. Klootsema, S. Rievers, E. D. Dijkstra (CSEM) and, E. Paaske,
J. Justesen, K. Larsen, J. Sparsø, and S. Pedersen (DTU).
Design and development of a very high speed Reed-Solomon
encoder/decoder chip set: Requirement analysis.
ESA/ESOC project no. 13.501 CSEM Technical Report 444, Centre
Suisse d'electronique et microtechnique S. A. and Technical
University of Denmark, May 1992.
106 pages. |
| [71] |
F. Bauduin, R. Klootsema, S. Rievers, E. D. Dijkstra (CSEM) and, E. Paaske,
J. Justesen, K. Larsen, J. Sparsø, and S. Pedersen (DTU).
Design and development of a very high speed Reed-Solomon
encoder/decoder chip set: Architectural design report.
ESA/ESOC project no. 13.501 CSEM Technical Report 496.I,
Centre Suisse d'electronique et microtechnique S. A. and Technical
University of Denmark, May 1992.
525 pages. |
| [72] |
J. Sparsø, J. Staunstrup, and M. Dantzer-Sørensen.
Design of delay insensitive circuits using multi-ring structures.
In G. Musgrave, editor, Proc. of EURO-DAC '92, European Design
Automation Conference, Hamburg, Germany, September 7-10, 1992, pages 15-20.
IEEE Computer Society Press, 1992. |
| [73] |
E. Paaske, S. Pedersen, and J. Sparsø.
An area-efficient path memory structure for VLSI implementation of
high speed Viterbi decoders.
INTEGRATION, the VLSI Journal, 12(2):79-91, November 1991. |
| [74] |
J. Sparsø, H. N. Jørgensen, E. Paaske, S. Pedersen, and
T. Rübner-Petersen.
An area-efficient topology for VLSI implementation of Viterbi
decoders and other shuffle-exchange type structures.
IEEE Journal of Solid State Circuits, SC-26(2):90-97, February
1991. |
| [75] |
J. Sparsø, S. Pedersen, and E. Paaske.
Design of a fully parallel Viterbi decoder.
In A. Halaas and P. B. Denyer, editors, Proc. of VLSI91, IFIP
TC10/WG10.5 International Conference on Very Large Scale Integration,
Edinburgh, Scotland, August 20-22, 1991, pages 29-39. North-Holland (IFIP
Transactions, vol. A-1), 1991. |
| [76] |
S. Pedersen and J. Sparsø.
Struktureret konstruktion af digitale ASIC's.
Technical Report ID-U/1991-42, Department of Computer Science,
Technical University of Denmark, 1991.
83 pages. |
| [77] |
J. Sparsø, H. N. Jørgensen, E. Paaske, S. Pedersen, and
T. Rübner-Petersen.
An area-efficient topology for VLSI implementation of Viterbi
decoders and other shuffle-exchange type structures.
Technical Report ID-TR:1990-71, Department of Computer Science,
Technical University of Denmark, May 1990. |
| [78] |
S. Pedersen and J. Sparsø.
Experiences from the design of a large VLSI chip.
In Proc. of NORCHIP/NORSILC seminar 1990, Lund, October
30 - November 1, 1990, pages 12.0-12.11, 1990. |
| [79] |
H. N. Jørgensen, E. Paaske, S. Pedersen, and J. Sparsø.
Design and inplementation of a full-custom single chip Viterbi
decoder.
In Proc. of NORCHIP/NORSILC seminar 1989, Stockholm, October
23-24, 1989, pages 13.0-13.9, October 1989. |
| [80] |
J. Sparsø, H. N. Jørgensen, E. Paaske, S. Pedersen, and
T. Rübner-Petersen.
A fully parallel VLSI-implementation of the Viterbi decoding
algorithm.
Technical Report ID-TR:1989-55, Department of Computer Science,
Technical University of Denmark, April 1989. |
| [81] |
J. Sparsø, H. N. Jørgensen, E. Paaske, S. Pedersen, and
T. Rübner-Petersen.
A fully parallel VLSI-implementation of the Viterbi decoding
algorithm.
In Proc. of ESSIRC'89, 15th European Solid State
Circuits Conference, Vienna, Austria, 20-22 September, 1989, pages
232-235, 1989. |
| [82] |
M. N. Jensen, M. Skov, and J. Sparsø.
Hardware architecture of a node for the LAN-DTH high speed token
ring.
In Proc. of EFOC/LAN 87 (Fifth Annual European Fibre Optic
Communications and Local Aera Networks Conference), Basel, Switzerland, June
3-5, 1987, pages 214-219, 1987. |
| [83] |
J. Sparsø.
A POLYNET to VME-bus Interface Unit - Block diagram and principles
of oparation (LAN-DTH project note 13).
Technical Report ID-1188, Department of Computer Science, Technical
University of Denmark, April 1986.
53 pages. |
| [84] |
J. Sparsø.
Hardware architecture of a node for the LAN-DTH high speed token
ring (LAN-DTH project note 8).
Technical Report ID-TR:1986-7, Department of Computer Science,
Technical University of Denmark, February 1986.
61 pages. |
| [85] |
M. N. Jensen, R. I. Sharp, M. Skov, and J. Sparsø.
LAN-DTH - A hierarchical local area network based on a high
speed optic token ring.
In Proc. of IFIP TC6/WG6.4 International In Depth
Symposium on Local Communication Systems LAN and PBX, Toulouse,
France, November 26-28, 1986, pages 339-351, 1986. |
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