Realistically Rendering SoC Traffic Patterns with Interrupt Awareness

AbstractIn Multi-Processor System-on-Chip (MPSoC) design
stages, accurate modeling of IP behaviour is crucial to
analyze interconnect effectiveness. However, parallel development
of components may cause IP core models to be
still unavailable when tuning communication performance.
Traditionally, synthetic traffic generators have been used
to overcome such an issue. However, target applications
increasingly present non-trivial execution flows and synchronization
patterns, especially in presence of underlying
operating systems and when exploiting interrupt facilities.
This property makes it very difficult to generate realistic test
traffic. This paper presents a selection of applications using
interrupt-based synchronization; a reference methodology
to split such applications in execution subflows and to
adjust the overall execution stream based upon hardware
events; a reactive simulation device capable of correctly
replicating such software behaviours in the MPSoC design
phase. Additionally, we validate the proposed concept by
showing cycle-accurate reproduction of a previously traced
application flow.
TypeConference paper [With referee]
ConferenceIFIP International Conference on Very Large Scale Integration (VLSI-SoC)
Year2005    Month September
BibTeX data [bibtex]
IMM Group(s)Computer Science & Engineering

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