@ARTICLE\{IMM2007-05059,
    author       = "S. F. Nielsen and J. Spars{\o} and J. Madsen",
    title        = "Behavioral synthesis of asynchronous circuits using syntax directed compilation as backend",
    year         = "2007",
    journal      = "{IEEE} Transaction on {VLSI} Systems",
    volume       = "",
    editor       = "",
    number       = "",
    publisher    = "",
    url          = "http://www2.compute.dtu.dk/pubdb/pubs/5059-full.html",
    abstract     = "This paper presents a method for behavioral synthesis
of asynchronous circuits which is very similar to
what is found in existing synchronous design tools: (i)
extraction of a {CDFG,} (ii) scheduling, allocation and
binding, and (iii) generation of a datapath and a controller.
The novelty is our approach used for enabling
standard behavioral synthesis algorithms to be used in
continous time and the way in we describe and generate
the datapath and the controller using Balsa, an
existing asynchronous synthesis tool based on syntax
directed compilation. Our approach has several advantages:
it provides synthesis from a higher level of
abstraction, it leverages on an existing tool flow for
generating and optimizing circuit level implementations,
and it generates the controller as a structure
of handshake components, thus avoiding the problems
related to synthesizing a single and often very complex
controller; a problem experienced in several other approaches.
The paper presents the different steps of the
synthesis method using a single running example. The
paper also reports on area, speed and power figures for
a range of benchmark circuits, of which a couple have
been synthesized to layout."
}