@CONFERENCE\{IMM2005-04166,
    author       = "G. Venkataramani and T. Bjerregaard and T. Chelcea and S. C. Goldstein",
    title        = "{SOMA} A Tool for Synthesizing and Optimizing Memory Accesses in ASICs",
    year         = "2005",
    month        = "sep",
    keywords     = "clockless, asynchronous, synthesis, ansi-c, memory access, network-on-chip",
    pages        = "231-236",
    booktitle    = "Proceedings of the {IEEE}/ACM/{IFIP} International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS'05)",
    volume       = "",
    series       = "",
    editor       = "",
    publisher    = "ACM",
    organization = "",
    address      = "",
    url          = "http://www2.compute.dtu.dk/pubdb/pubs/4166-full.html",
    abstract     = "Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale {ASIC} systems in high-level synthesis. This paper presents {SOMA,} a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent
accesses to a shared memory resource. To alleviate this bottleneck, {SOMA} uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the {MAN} architecture. Depending on the parallelism profile, the {MAN} may be optimized for latency, throughput or both. The optimized {MAN} 
is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. {SOMA} has been successfully integrated into an automated {C-}to-hardware synthesis flow, which generates standard cell circuits from unrestricted {ANSI-C} programs. Post-layout experiments demonstrate that application specific {MAN} construction significantly improves power and performance."
}