@CONFERENCE\{IMM2005-04082,
    author       = "H. Holten-Lund",
    title        = "Embedded {3D} Graphics Core for {FPGA-}based System-on-Chip Applications",
    year         = "2005",
    month        = "sep",
    keywords     = "{FPGA,} System-On-Chip, {3D} Graphics",
    pages        = "8-13",
    booktitle    = "FPGAworld conference 2005",
    volume       = "",
    series       = "",
    editor       = "Lennart Lindh and Vincent J. Mooney {III}",
    publisher    = "Electrum-Kista",
    organization = "",
    address      = "Stockholm, Sweden",
    note         = "{ISRN} {MDH-MRTC-}188/2005-1-SE",
    url          = "http://www.fpgaworld.com",
    abstract     = "This paper presents a {3D} graphics accelerator core for an {FPGA} based system, and illustrates how to build a System-on-Chip containing a Xilinx MicroBlaze soft-core {CPU} and our {3D} graphics accelerator core. The system is capable of running uClinux and hardware accelerated {3D} graphics applications such as a {VRML} viewer. 
The {3D} graphics core is connected to a {PLB} 64-bit on-chip bus, and can render graphics into an on-chip tile buffer, which is later copied, using bus-master {DMA} transfers, to the frame-buffer in external {DDR} {SDRAM} memory. This memory is shared between the {CPU,} the {3D} graphics core, and the video display which periodically reads from memory to display the final rendered graphics. The graphics core uses internal scratch-pad memory to reduce its external bandwidth requirement, this is achieved by implementing a tile-based rendering algorithm. Reduced external bandwidth means that the power consumption is reduced as well. 

We show how an {FPGA} based embedded system is capable of most tasks in a single chip solution, without requiring additional {CPU} or graphics chips.",
    isbn_issn    = "{ISSN} 1404-3041"
}