@CONFERENCE\{IMM2005-03917,
    author       = "S. Mahadevan and F. Angiolini and M. Storgaard and R. Olsen and J. Spars{\o} and J. Madsen",
    title        = "A Network Traffic Generator Model for Fast Network-on-Chip Simulation",
    year         = "2005",
    month        = "mar",
    pages        = "780-785",
    booktitle    = "Design, Automation and Test in Europe",
    volume       = "",
    series       = "",
    editor       = "Nobert Wehn and Luca Benini",
    publisher    = "",
    organization = "",
    address      = "",
    url          = "http://www2.compute.dtu.dk/pubdb/pubs/3917-full.html",
    abstract     = "For Systems-on-Chip (SoCs) development, a predominant part of the design time is the simulation time. Performance evaluation and design space exploration of such systems in bit- and cycle-true fashion is becoming prohibitive. We propose a traffic generation (TG) model that provides a fast and effective Network-on-Chip (NoC) development and debugging environment. By capturing the type and the timestamp of communication events at the boundary of an {IP} core in a reference environment, the {TG} can subsequently emulate the core's communication behavior in different environments. Access patterns and resource contention in a system are dependent on the interconnect architecture, and our {TG} is designed to capture the resulting reactiveness. The regenerated traffic, which represents a realistic workload, can thus be used to undertake faster architectural exploration of interconnection alternatives, effectively decoupling simulation of {IP} cores and of interconnect fabrics. The results with the {TG} on an {AMBA} interconnect show a simulation time speedup above a factor of 2 over a complete system simulation, with close to 100\% accuracy."
}