@MASTERSTHESIS\{IMM2013-06552,
    author       = "E. Lakis",
    title        = "{FPGA} Implementation of a Time Predictable Memory Controller for a Chip-Multiprocessor System",
    year         = "2013",
    school       = "Technical University of Denmark, {DTU} Compute, {E-}mail: compute@compute.dtu.dk",
    address      = "Matematiktorvet, Building 303{-B,} {DK-}2800 Kgs. Lyngby, Denmark",
    type         = "",
    note         = "{DTU} supervisor: Martin Schoeberl, masca@dtu.dk, {DTU} Compute.",
    url          = "http://www.compute.dtu.dk/English.aspx",
    abstract     = "The use of modern conventional architectures in real-time systems (RTS) requires complex analysis and suffers from high resource over-allocation needed to cover uncertainties stemming from employed speculative, average case optimizations. The design of time predictable {RTS} optimized architectures that allow easy timing analysis and tight timing guaranties is an active research topic.
The goal of this thesis is to explore the options for a predictable {SDRAM} controller for the {T-CREST} platform. The {T-CREST} project is an ongoing research project supported by the European Union’s 7th Framework Programme, aiming to develop a homogeneous time-predictable multi-processor platform. The variable {SDRAM} access latencies pose some challenges for its effective use in {RTS,} while the many-core {T-CREST} platform creates a new context for rethinking the previous results and finding the new solutions for external memory access.
The simple working prototype of the single-port {SDRAM} controller is implemented and integrated with the processor. Several options for multi-port arbitration are considered, and proposal is made for arbitration and interconnect in {T-CREST} project. We evaluate our controller and make a closer look at one state of the art controller for {RTS}."
}