@MASTERSTHESIS\{IMM2012-06468,
    author       = "B. Petersen",
    title        = "{FPGA} Signal Preprocessing for Digital Wireless Receivers",
    year         = "2012",
    school       = "Technical University of Denmark, {DTU} Informatics, {E-}mail: reception@imm.dtu.dk",
    address      = "Asmussens Alle, Building 305, {DK-}2800 Kgs. Lyngby, Denmark",
    type         = "",
    note         = "{DTU} supervisor: Alberto Nannarelli, an@imm.dtu.dk, {DTU} Informatics",
    url          = "http://www.imm.dtu.dk/English.aspx",
    abstract     = "This thesis deals with the task of exchanging analog filters with digital filters. These analog filters, used in a base station receiver for wireless communication, have the job of filtering incoming {TETRA} and {TEDS} signals for unwanted channels and blockers. Analysis performed in this thesis based on a set of requirements for the filter process, have concluded that the best  filter type for the digital filter is {FIR} filters of a symmetric structure. 
In order to apply {FIR} filters, a  flexible filter architecture has been designed and implemented as an {RTL} hardware model with {VHDL}. Digital filtering can be broken down to a sum of additions and multiplications. Since embedded multipliers are limited in FPGAs the designed architecture is based on a resizeable parallel and sequential part which allows it to make the best use of the multipliers taken the desired clock frequency into account. The architecture supports symmetric {FIR} filters of an odd order number. The order can vary from 7 to 575 in predefined steps. A suitable {FPGA} is necessary to implement filters of high orders.
This architecture has been used to implement a set of single and dual carrier systems based on filters of order 383 on a Spartan 3 {FPGA}.
In order to test the system, the architecture has been surrounded by an environment consisting of a set of interfaces enabling the system to receive incoming data from an {ADC} and send filtered data to a pc for further analysis. Through this, the filter architecture was verified and the implemented filters tested successfully."
}