@MASTERSTHESIS\{IMM2012-06321,
    author       = "G. Papanikas",
    title        = "Real-time Automatic Transcription of Drums Music Tracks on an {FPGA} Platform",
    year         = "2012",
    school       = "Technical University of Denmark, {DTU} Informatics, {E-}mail: reception@imm.dtu.dk",
    address      = "Asmussens Alle, Building 305, {DK-}2800 Kgs. Lyngby, Denmark",
    type         = "",
    note         = "Supervised by Associate Professor Alberto Nannarelli, an@imm.dtu.dk, {DTU} Informatics",
    url          = "http://www.imm.dtu.dk/English.aspx",
    abstract     = "Regarding the hardware implementation, the performance of the system meets the expected one, since the vast majority of strokes are correctly recognized. Unrecognized strokes are more frequent in case of simultaneous strokes on at least two instruments. The tests were performed on the same drum kit, using the simulation's fixed basis matrix of the same kit's recordings.
Regarding the specific {NNMF-}based approach, it has been shown, in both real's and simulation's results, that it behaves very reliably. In case more than one components per source are used, the transcription is reliable even with more instruments present. It could form a very computationally effective, automatic transcription system, together with an algorithm that combines the various components' information, in order to extract the correct onsets. However, even the minimal core that was implemented could be used, without further additions, to implement a tempo tracker system; that is a system which focuses only on snare and bass drums, in order to extract the variations in tempo during a drumming performance.
Evaluating the work on the thesis project in general, very useful experience was gained on {VHDL} programming, a main thesis project's motivation. In addition, approaching the automatic transcription problem from scratch, the literature survey, and building an {FPGA} ”friendly” system has been an invaluable, instructive experience. A very important lesson taught regards to the debugging procedure of the {VHDL} code. Surprisingly, at some premature tests the system worked for the first time, although bugs were present in various stages of the data flow. The performance was very poor, barely half of the strokes were recognized, but the fact that it showed that it is working was misleading itself. In the sense that this poor performance was pointing to possible bugs at some fixed-point calculations, where errors in following the radix point, or manipulating the data word widths, may easily lead to not so critically erroneous behavior. Indeed there were such bugs, whose corrections though had the opposite effect to system's performance. Until a bug at the very first stage of the algorithm was found and, as always, regarded the simplest thing; that was a wrong configuration bit for the {CODEC'}s registers, that resulted to a wrong frequency in the clocks of {ADC} controller."
}