@MASTERSTHESIS\{IMM2012-06291,
    author       = "C. L. Andersen",
    title        = "Cache for reducing power consumption of a hearing instrument",
    year         = "2012",
    school       = "Technical University of Denmark, {DTU} Informatics, {E-}mail: reception@imm.dtu.dk",
    address      = "Asmussens Alle, Building 305, {DK-}2800 Kgs. Lyngby, Denmark",
    type         = "",
    note         = "Supervised by Associate Professor Alberto Nannarelli, an@imm.dtu.dk, {DTU} Informatics, and supervisor {GNR}: Kai Harrekilde-Petersen, and Kashif Virk",
    url          = "http://www.imm.dtu.dk/English.aspx",
    abstract     = "Power consumption have and may all ways be a issue when designing hearing aid. Today the functionality in a hearing aid is much more the a couple of filter and an amplifier. And with the introduction of wireless communication to and from a hearing aid the requirement for power keeps growing. There by the need to save power where ever it is possible get more importen. In a system with a processor a significant part of the power is used to fetch instruction and data from memory. Fetching from a big memory cost more power then fetching from a small memory. Do this mean that the processor system is able to save power all over by adding a small cache to its memory system?
This thesis will show how a software model of a processors memory system. Along the model a file containing an address and data trace for same processor system. These two combined can be used to predict the behaviour of same system with different caches. By adding a cost function for cache hit, miss ect. it is the hope the model can calculate which cache result the lowest total power use.
First the software model is designed and build, for its result 3 caches is chosen, for implementation in {VHDL}. From power simulation of the {VHDL} the actual power use of these caches is found. The models result is the compared to this numbers."
}