Analyzing for Absence of Timing Leaks in VHDL

Analyzing for Absence of Timing Leaks in VHDL
Terkel K. Tolstrup, Flemming Nielson
Type	Conference paper [With referee]
Conference	Conference
Year	2006
Publisher	WITS'06
BibTeX data	[bibtex]
IMM Group(s)	Computer Science & Engineering