Multiprocessor in a FPGA |
| | Abstract | Computer chips are becoming increasingly more complicated with whole systems and multiple processors on a single chip. I have design and implements such a SoC with multiple processors.
To keep down the work load, the processor and some peripheral units are taken from the community at OpenCores.org. This will ensure that no problems with the processor occur since this have been tested thoroughly and is known to work. The same applies for the UART which is used to verify that the system runs correctly at the FPGA. These uses a WISHBONE interface and therefor this have been adapted.
Synchronization unit and network component have been designed from scratch. Within the network aspect such as routing- and forwarding strategy has to be decided along with typology designs.
The design process have been split up in five steps, starting with just a connection between memory and processor, each step adding a new aspect. At the end a multiprocess system which uses NoC are designed. Two different network typologies have been designed thereby making two systems with NoC. Additionally a bus from the OpenCores community have been used, to design a multiprocessor system. The bus have been tested and proven working, which means that it can be used to verify everything else works as intended in a multiprocessor system, before the NoC was developed.
Finally the result from the multiprocessor systems are discussed and compared to find out how well the designed NoCs are working and what could be done better. | | Type | Bachelor of Engineering thesis [Academic thesis] | | Year | 2007 | | Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU | | Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby | | Series | IMM-B.Sc-2007-10 | | Note | | | Electronic version(s) | [pdf] | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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