Compiling from Haste to CDFG: a front end for an asynchronous circuit synthesis system | Jonas Braband Jensen, Johan Sebastian Rosenkilde Nielsen
| | Abstract | We have implemented a compiler from the high-level asynchronous hardware programming language Haste into a control-data flow graph, or CDFG. The CDFG representation is used in the literature for scheduling and resource sharing optimisations in hardware synthesis.
There exists a multitude of CDFG dialects in the literature, none of them directly suitable for representing Haste, which has CSP-like parallel processes and channel communication. Therefore we have designed our own dialect, and we compare it to three prominent dialects from the literature.
The compiler translates a non-trivial subset of Haste into this dialect using the intermediate language Hurry as a stepping stone. In designing Hurry, our goal was to simplify Haste to the greatest extent possible without losing descriptive power or introducing inefficiencies. The resulting reduction in complexity makes Hurry suitable not just for this project, but any system analysing Haste code should consider using Hurry as an intermediate representation.
We have implemented a simulator for our CDFG dialect, and therefore a simulator for Haste. This enabled us to test the compiler with both real-world programs and unit tests that exercise corner cases of the language.
We have looked the possibility of performing optimisations on a CDFG, and we describe problems that arise when we impose no well-formedness restrictions on it. | | Type | Bachelor of Engineering thesis [Academic thesis] | | Year | 2007 | | Publisher | Informatics and Mathematical Modelling, Technical University of Denmark, DTU | | Address | Richard Petersens Plads, Building 321, DK-2800 Kgs. Lyngby | | Series | IMM-B.Sc-2007-08 | | Note | | | Electronic version(s) | [pdf] | | BibTeX data | [bibtex] | | IMM Group(s) | Computer Science & Engineering |
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