A New Way Of Estimating Compute Boundedness And Its Application To Dynamic Voltage Scaling |
Vasanth Venkatachalam, Christian W. Probst, Michael Franz
|
| Abstract | Many recent dynamic voltage-scaling (DVS) algorithms use hardware events (such as cache misses, memory bus transactions, or instruction execution rates) as the basis for deciding how much a program region can be slowed down with acceptable performance loss. Although these approaches result in power savings, the hardware events measured are at best indirectly related to execution time and clock frequency. We propose a new metric for evaluating the performance loss caused by DVS, a metric that is logically related to clock frequency and execution time, namely the percentage drop in cycles. Further, we show that we can predict with high accuracy the execution time of a code region at any clock frequency after measuring the total number of cycles spent in that region for two clock frequencies---the maximum and the second highest clock frequency. Measurements using several real-world applications show that this "two-point'' model predicts execution times with an accuracy that is greater than 95% in many cases. This result can be used to develop low-overhead DVS algorithms that are more system-aware than many of the current algorithms, which rely on measuring indirect effects. |
| Keywords | dynamic voltage scaling, performance prediction, power consumption |
| Type | Journal paper [With referee] |
| Journal | International Journal of Embedded Systems |
| Year | 2006 Vol. 1 No. 1 pp. 64-74 |
| Electronic version(s) | [pdf] |
| BibTeX data | [bibtex] |
| IMM Group(s) | Computer Science & Engineering |