| Abstract | The design of Multi-Processor Systems-on-Chip (MP-SoCs)
emphasizes Intellectual Property (IP) based
communication-centric approaches. Therefore, for the op-timization
of the MPSoC interconnect, the designer must
develop traffic models that realistically capture the appli-cation
behaviour as executing on the IP core. In this paper,
we introduce a Reactive Intellectual Property Emulator
(RIPE) that enables an effective emulation of the IP
core behaviour in multiple (including bit- and cycle-true
simulation) environments. The RIPE is built as a multi-threaded
abstract instruction set processor and it can
generate reactive traffic modeling. We compare the RIPE
models with cycle-true functional simulation of complex
application behaviour (task synchronization, multitasking,
input/output operations). Our results demonstrate high
accuracy and significant speedups. Further, via a case
study we show the potential use of the RIPE in a design
space exploration context. |