| Abstract | In highly parallel Multi-Processor System-on-Chip (MPSoC) design
stages, interconnect performance is a key optimization target. To effectively
achieve this objective, true-to-life IP core traffic must be injected and analyzed.
However, the parallel development of MPSoC components may cause IP core
models to be still unavailable when tuning communication performance. Tradi-tionally,
synthetic traffic generators have been used to overcome such an issue.
However, target applications increasingly present non-trivial execution flows
and synchronization patterns, especially in presence of underlying operating sys-tems
and when exploiting interrupt facilities. This property makes it very diffi-cult
to generate realistic test traffic. This paper presents a selection of applica-tion
flows, representative of a wide class of applications with complex interrupt-based
synchronization; a reference methodology to split such applications in
execution subflows and to adjust the overall execution stream based upon hard-ware
events; a reactive simulation device capable of correctly replicating such
software behaviours in the MPSoC design phase. Additionally, we validate the
proposed concept by showing cycle-accurate reproduction of a previously traced application flow. |