@MASTERSTHESIS\{IMM2005-03974,
    author       = "M. B. Stensgaard",
    title        = "Design of an asynchronous communication network for an audio {DSP} chip",
    year         = "2005",
    school       = "Informatics and Mathematical Modelling, Technical University of Denmark, {DTU}",
    address      = "Richard Petersens Plads, Building 321, {DK-}2800 Kgs. Lyngby",
    type         = "",
    note         = "Supervised by Assoc. Prof. Jens Spars{\o}",
    url          = "http://www2.compute.dtu.dk/pubdb/pubs/3974-full.html",
    abstract     = "This project investigates the replacement of the communication network in a multi-configurable {DSP-}core developed by William Demant Holding. The existing network is implemented as a subset of a fully connected network which contains many long wires that consume power and complicates routing.

The existing network is replaced by 3 different packet-switched, source-routed asynchronous networks, which solve many of the problems in the current network implementation. The size of the networks are linear with the number of communicating blocks which makes it very scalable, the networks are 'plug-and-play' and can be ported to other applications, there are no restrictions on which blocks that can communicate as in the current solution, and the networks decouple the connected blocks which allows them to run in their own clock domain.

As the needed bandwidth is very low the networks are designed with area and power in mind, and simple solutions are chosen for all design issues. The networks are implemented as a binary tree of merger and router blocks, and both bundled data and a {1-}of-5 delay-insensitive data encoding are implemented and compared.

This report documents the design, implementation, synthesis, and verification of the networks. It also discusses the design choices in a number of different areas such as data-encoding, network topology and how to implement multicasting. As the networks are designed as asynchronous circuits, part of the report documents the implementation of these and how to handle asynchronous circuits in a synchronous design flow."
}