@MASTERSTHESIS\{IMM2003-02522,
    author       = "K. Wu",
    title        = "Optimal algorithms for {GSM} Viterbi modules",
    year         = "2003",
    keywords     = "Convolutional decoder, Viterbi algorithm, Low power, Low area, {VLSI,} {GSM}",
    school       = "Informatics and Mathematical Modelling, Technical University of Denmark, {DTU}",
    address      = "Richard Petersens Plads, Building 321, {DK-}2800 Kgs. Lyngby",
    type         = "",
    note         = "Supervisor: Flemming Stassen",
    url          = "http://www2.compute.dtu.dk/pubdb/pubs/2522-full.html",
    abstract     = "A power/area optimum design of the 3rd-Generation Global System for Mobile communications({GSM} {3G}) unit's channel code decoder has been described. This decoder can perform the convolutional code decoding and the {CRC} check for a burst of transmitted data encoded by other {GSM} {3G} units. The constraint length of the decoder varies between 5 and {7,} the code rate varies from 2 to {6,} and the received data are calibrated into 4 or {5-}bit soft-decision bits. The power and area optimization is only considered at the algorithm and architecture level. The power/area effciency is measured from the gatelevel synthesis result. When the decoder is clocked at 100MHz and is given a 1.{3V} voltage supply, the measurement results show that the decoder's power consumption is typically less than 1.4mW. The decoder core consists of approximately 35.7 k gates (142.8 k transistors), which is equivalent to the area of 0:24mm 2 for the given 0.09 µm {5-}metallayer {CMOS} technology."
}